ASIC Verification Engineer

Broadcom • Fort Collins, CO

1d

About The Position

We are seeking a highly skilled ASIC Verification Engineer to design, implement, and maintain advanced verification infrastructure across a diverse portfolio of ASIC products. The role collaborates with design teams to develop verification plans, build reusable testbenches, and scale verification coverage to help ensure first-pass silicon success.

The engineer will architect verification environments using SystemVerilog and UVM; develop modular components such as reference models, checkers, monitors, scoreboards, and targeted firmware; analyze architectural specifications; create and debug directed and constrained-random tests; and track functional and code coverage. The role also uses SystemVerilog Assertions to catch corner-case design bugs, manages design databases and official releases, and oversees automated regression runs, failure triage, and performance tracking.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, with at least 8 years of relevant ASIC verification experience; or a master’s degree in a related field with at least 6 years of relevant ASIC verification experience.
• Strong proficiency in SystemVerilog, Verilog coding, and SystemVerilog Assertions (SVA).
• Strong programming skills in C/C++.
• Scripting expertise in Python, Perl, or Tcl for environment automation and regression sorting.

Nice To Haves

• Hands-on experience building testbenches from scratch using the Universal Verification Methodology (UVM).
• Deep understanding of the front-to-back ASIC design and verification lifecycle, including pre-silicon simulation, debugging, and coverage closure.
• Familiarity with ARM processor architectures and AMBA subsystem protocols such as AXI, AHB, and APB.
• Exposure to Digital Signal Processing (DSP) algorithms and translating them into hardware verification reference models.

Responsibilities

• Architect and develop robust, scalable, reusable verification environments using SystemVerilog and UVM.
• Create modular verification components, including reference models, checkers, monitors, scoreboards, and targeted firmware code.
• Develop detailed verification plans by analyzing architectural specifications.
• Develop, execute, and debug directed and constrained-random test cases for complex ASIC IP blocks.
• Track, analyze, and maximize functional and code coverage metrics.
• Write SystemVerilog Assertions (SVA) for assertion-based verification and detection of corner-case design bugs.
• Establish, maintain, and optimize processes for design database management and official database releases.
• Oversee automated daily and weekly regression runs, triage failures, and manage performance tracking.

Benefits

• Discretionary annual bonus.
• Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior