ASIC Emulation & Verification Engineer

Broadcom • San Jose, CA

1d

About The Position

Broadcom is seeking an experienced ASIC Emulation and Verification Engineer to bridge simulation and hardware acceleration. The role focuses on bringing up complex ASIC IP and SoC designs on Cadence Palladium emulation platforms, converting RTL databases into emulation-ready models, and running high-speed hardware acceleration. The engineer will also support the pre-silicon team through UVM-based simulation, verification closure, and debugging.

The position partners with firmware engineers to enable early firmware bring-up on Palladium, including providing hardware models, mapping memory spaces, and configuring virtual debuggers such as JTAG. This allows teams to boot low-level bootloaders, drivers, and operating systems before physical silicon is available.

Minimum qualifications are a bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field and at least 8 years of hardware description or verification experience, or a master’s degree in a related field and at least 6 years of relevant experience. The posting lists an annual base salary range of USD 121,900 to USD 195,000, with eligibility for a discretionary annual bonus and new-hire and annual equity awards.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field and a minimum of 8 years of hardware description or verification experience; alternatively, a master’s degree in a related field and a minimum of 6 years of relevant experience.
• Strong proficiency in Verilog and SystemVerilog and understanding of hardware synthesis concepts for emulation mapping.
• Proven experience with UVM simulation frameworks, assertion-based testing (SVA), and metric-driven coverage closure.
• Expertise in Python, Perl, Bash, or Tcl for log parsing, compiler-tool automation, and regression database management.
• Solid understanding of AMBA subsystem protocols (AXI, AHB, APB) and processor interfaces for configuring memory and clock domains in an emulator.

Nice To Haves

• Deep hands-on experience with Cadence Palladium enterprise emulation platforms, such as Palladium Z1/Z2 or newer systems.

Responsibilities

• Compile, synthesize, and map complex RTL databases onto Cadence Palladium hardware acceleration systems.
• Resolve compilation errors, manage clocking and memory overrides, and bring up full-chip and subsystem emulation models.
• Partner with firmware engineering teams to accelerate early firmware bring-up on Palladium.
• Provide hardware models, map memory spaces, and configure virtual debuggers such as JTAG to support booting bootloaders, drivers, and operating systems before physical silicon is available.
• Perform pre-silicon verification using SystemVerilog and UVM.
• Author test cases, develop monitors and checkers, and debug RTL anomalies using waveform viewers.
• Diagnose hardware, testbench, and environment issues on Palladium and root-cause failures across simulation and emulation environments.
• Build and maintain scripts to compile RTL databases and launch Palladium regressions.
• Manage database hand-offs between design release teams and the emulation environment.

Benefits

• Discretionary annual bonus eligibility
• Competitive new-hire equity grant and annual equity awards
• Medical, dental, and vision plans
• 401(k) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave and vacation time
• Paid family leave and other leaves of absence in accordance with applicable laws

What This Job Offers

• Job Type: Full-time
• Career Level: Senior