ASIC Emulation & Verification Engineer

Broadcom • San Jose, CA

2d • $121,900 - $195,000

About The Position

Broadcom is seeking an experienced ASIC Emulation and Verification Engineer to bridge simulation and hardware acceleration. The role focuses on bringing up complex ASIC IP and SoC designs on Cadence Palladium emulation platforms, converting RTL databases into emulation-ready models, and executing high-speed hardware acceleration. The engineer will also support the pre-silicon team with UVM-based simulation, verification closure, and debugging.

The position works closely with firmware engineering teams to enable early firmware bring-up on Palladium, providing hardware models, mapping memory spaces, and configuring virtual debuggers such as JTAG so teams can boot low-level bootloaders, drivers, and operating systems before physical silicon is available. It also involves automating RTL compilation and Palladium regressions, diagnosing issues across simulation and emulation environments, and managing database hand-offs.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field and at least 8 years of hardware description or verification experience; alternatively, a master’s degree in a related field and at least 6 years of relevant experience.
• Strong proficiency in Verilog and SystemVerilog.
• Knowledge of hardware synthesis concepts for emulation mapping.
• Experience with UVM simulation frameworks, assertion-based testing (SVA), and metric-driven coverage closure.
• Expertise in Python, Perl, Bash, or Tcl for log parsing, compiler-tool automation, and regression database management.
• Solid understanding of AMBA subsystem protocols, including AXI, AHB, and APB, and processor interfaces.

Nice To Haves

• Deep hands-on experience with Cadence Palladium enterprise emulation platforms, such as Palladium Z1/Z2 or newer systems.

Responsibilities

• Compile, synthesize, and map complex RTL databases onto Cadence Palladium hardware acceleration systems.
• Resolve compilation errors, manage clocking and memory overrides, and bring up full-chip and subsystem emulation models.
• Partner with firmware teams to accelerate early firmware bring-up on Palladium.
• Provide hardware models, map memory spaces, and configure virtual debuggers such as JTAG to support bootloader, driver, and operating-system bring-up.
• Perform pre-silicon verification using SystemVerilog and UVM, including authoring test cases, developing monitors and checkers, and debugging RTL anomalies with waveform viewers.
• Diagnose hardware, testbench, and environment issues on Palladium and root-cause failures across simulation and emulation.
• Build and maintain scripts to compile RTL databases and launch Palladium regressions.
• Manage database hand-offs between design release teams and the emulation environment.

Benefits

• Discretionary annual bonus.
• Competitive new-hire equity grant and potential annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior