ASIC Verification Engineer

Broadcom • Fort Collins, CO

2d • $109,700 - $175,500

About The Position

Broadcom is seeking an ASIC Verification Engineer to design, implement, and maintain verification infrastructure across its ASIC product portfolio. The engineer will work with design teams to develop verification plans, build reusable testbenches, and scale verification coverage to support first-pass silicon success.

The role includes developing SystemVerilog and UVM verification environments and components; planning and executing directed and constrained-random tests; analyzing coverage and implementing assertion-based verification; and managing design databases and regression processes. The engineer will oversee automated regression runs, triage failures, and track performance.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and at least 8 years of relevant ASIC verification experience; alternatively, a master’s degree in a related field and at least 6 years of relevant ASIC verification experience.

Nice To Haves

• Strong proficiency in SystemVerilog, Verilog coding, and SystemVerilog Assertions (SVA).
• Hands-on experience building testbenches from scratch using the Universal Verification Methodology (UVM).
• Deep understanding of the front-to-back ASIC design and verification lifecycle, including pre-silicon simulation, debugging, and coverage closure.
• Familiarity with ARM processor architectures and AMBA subsystem protocols such as AXI, AHB, and APB.
• Exposure to Digital Signal Processing (DSP) algorithms and translating them into hardware verification reference models.
• Strong programming skills in C/C++ and scripting expertise in Python, Perl, or Tcl for environment automation and regression sorting.

Responsibilities

• Architect and develop robust, scalable, reusable verification environments using SystemVerilog and UVM.
• Create modular verification components, including reference models, checkers, monitors, scoreboards, and targeted firmware code.
• Analyze architectural specifications and author detailed verification plans.
• Develop, execute, and debug directed and constrained-random tests for complex ASIC IP blocks.
• Track, analyze, and maximize functional and code coverage metrics.
• Write SystemVerilog Assertions (SVA) for assertion-based verification and to detect corner-case design bugs.
• Establish, maintain, and optimize design database management processes and official database releases.
• Oversee automated daily and weekly regression runs, triage failures, and manage performance tracking.

Benefits

• Discretionary annual bonus eligibility.
• Opportunity to receive a competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior