Design Verification Engineer

Broadcom • San Jose, CA

19d

About The Position

The ASIC Product Division at Broadcom is seeking a Design Verification Engineer to join a high-performance design team developing state-of-the-art SoC and IP subsystems to meet customer requirements. The role focuses on verifying designs at system and block levels, building verification environments and components, creating tests, and analyzing simulation and coverage results.

The position requires at least 12 years of relevant industry experience and a bachelor's degree in Electrical and Electronic Engineering, Computer Science, or an equivalent field. Candidates must be authorized to work in the United States. Experience with hardware design and debug, C++/SystemC, emulators, FPGA-based prototyping, chip design methodologies and tools, and CPU, DDR, bus, network, or DSP design is preferred.

The annual base salary range is listed as “USD To USD,” with no amounts provided. The role is eligible for a discretionary annual bonus, new-hire and annual equity awards, and Broadcom's benefits package. Broadcom is an equal opportunity employer.

Requirements

• Bachelor’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
• 12 or more years of relevant industry work experience.
• Experience verifying designs at system and block levels.
• Fluent knowledge of RTL verification methodologies, including SystemVerilog.
• Strong experience with ASIC design verification flows and design verification methodologies.
• Strong working knowledge of object-oriented verification languages such as OVM and UVM, C/C++, Perl, and scripting.
• Strong independent design-debugging capability.
• Strong verbal and written communication skills, and comfort working with verification and design team members.
• Demonstrated ability to analyze and resolve complex verification trade-off scenarios.
• Highly productive individual contributor with demonstrated technical capability in system- and sub-block-level verification.
• Legal authorization to work in the United States.

Nice To Haves

• Experience with hardware design and debug, C++/SystemC, and other programming languages.
• Experience working with emulators and FPGA-based prototyping.
• Familiarity with overall chip design methodologies and tools.
• Knowledge of CPU, DDR, bus protocol, network protocol, or DSP design.

Responsibilities

• Develop verification environments using modern verification techniques, including SystemVerilog and UVM.
• Design verification components such as UVM agents and behavioral models.
• Implement coverage and assertions using SystemVerilog.
• Develop random and directed test cases based on specifications.
• Analyze and debug simulation failures and analyze coverage results.

Benefits

• Discretionary annual bonus.
• Competitive new-hire equity grant and opportunity to receive annual equity awards.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior