Design Verification Engineer

MatX•Mountain View, CA

9h•Hybrid

About The Position

MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon verification engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies.

Requirements

Concept-to-silicon experience in driving verification from an architecture and/or design specification to production silicon
Experience with SystemVerilog, Python, C/C++, Bluespec and similar scripting and programming languages for verification and silicon modeling
Production experience with advanced verification methodologies such as UVM, assertion-based verification (ABV); experience and comfort with formal and simulated verification are required
Production experience with creating portable tests and drivers for verification that apply to silicon validation and post-silicon debug
Strong understanding of silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities
Authorized to work in the United States
Must work from our offices in Mountain View Tuesdays-Thursdays
Capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities

Nice To Haves

Familiarity with emulation and prototyping platforms and methodologies is a plus
Hands-on experience with participation in silicon debug and bring-up is a plus

Responsibilities

Contribute to MatX’s verification methodology with a scalable solution across blocks, subsystems, fullchip and system-level validation
Own portions of verification execution at subsystem and chip-level and create testbenches, tests and related artifacts to achieve structural and functional coverage closure
Plan and drive intermediate and sign-off reviews on verification test plans, execution progress and verification closure towards various silicon milestones including design freeze and tapeout