Design Verification Engineer - Accelerators

Meta•San Diego, CA

6d•$178,000 - $250,000

About The Position

Meta is hiring a Design Verification lead for custom silicon used in its AR glasses. The silicon supports computer vision, machine learning, imaging, and sensing while operating within a tight power budget. The role owns verification for complex computer vision and imaging accelerator IP and subsystems, defines verification strategy across multiple IPs, and builds reusable DV infrastructure that scales across chips and programs.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, a related technical field, or equivalent practical experience.
8+ years of hands-on verification experience with SystemVerilog, UVM, and C/C++ at the IP, subsystem, and SoC levels.
Experience leading design verification for complex IP or an SoC through tape-out, including ownership of sign-off.
Experience defining and executing verification plans, coverage strategies, and closure metrics, including functional and code coverage, across multiple blocks or IPs.
Experience building UVM verification environments from scratch and designing reusable verification components.
Deep experience in at least one of formal verification, SystemVerilog Assertions (SVA), emulation or FPGA prototyping, or low-power (UPF) verification.
Strong scripting skills in Python, TCL, Perl, or Shell for building verification tools and flows.
Experience leading and mentoring engineers and coordinating work across teams.

Nice To Haves

Experience verifying power-limited mobile, wearable, or AR/VR SoCs.
Experience managing EDA vendors or contracted DV teams.
Experience verifying computer vision, imaging/ISP, DSP, or ML accelerator designs.
Master's or PhD in EE, CE, or CS.
Experience rolling out methodology changes across an organization, including formal, emulation, portable stimulus, or ML/AI-assisted verification.
Experience verifying hardware against reference models written in C++ or Python, or co-simulating with firmware or software.
Experience scaling DV infrastructure, such as regression farms, CI for hardware, and coverage and triage dashboards, across multiple IPs or programs.

Responsibilities

Shape architecture and microarchitecture decisions with architecture, design, firmware/software, emulation, physical design, and post-silicon teams to ensure the chip is designed with verification in mind; coordinate schedules and sign-off criteria with TPMs.
Own design verification for multiple complex IPs or subsystems from verification planning through coverage closure and sign-off.
Define verification strategy across IPs, including the use of constrained-random simulation, UVM, formal verification, assertions, emulation, FPGA prototyping, and power-aware verification using UPF.
Design reusable testbench architectures, verification IP, and libraries for use across IPs, subsystems, and SoC generations.
Drive regression management, automated triage, coverage analytics, and compute-efficient simulation and emulation runs to sustain team throughput as the number of designs grows.
Identify verification-quality and productivity gaps, lead initiatives to improve quality and time-to-closure, and advance DV methodology, including AI-assisted methods.
Root-cause failures to specific lines of RTL, reference models, or firmware/software and propose fixes.