Design Verification Engineer

Apple•Waltham, MA

13d

About The Position

The Design Verification Engineer will help enable fully functional first silicon for IP designs and ensure bug-free first silicon for part of the SoC or IP. The role covers pre-silicon verification, including establishing verification methodology, developing test plans and scalable, portable verification environments, writing tests, debugging, tracking coverage, and signing off for RTL freeze and tape-out. The engineer will develop detailed test and coverage plans based on microarchitecture and build verification environments with components such as stimulus, checkers, assertions, trackers, and coverage. Responsibilities also include bringing up designs and DV environments, enabling regressions, executing verification plans, debugging failures, and developing block-, IP-, and SoC-level testbenches. The engineer will track and report DV progress using metrics such as bugs and coverage, and use LLMs and related technologies to improve execution efficiency and quality.

Requirements

Bachelor’s degree in a technical subject area and a minimum of 10 years of relevant industry experience, or equivalent.
Deep knowledge of object-oriented programming, SystemVerilog, and UVM.
Deep knowledge of developing scalable and portable testbenches.
Strong experience with verification methodologies and tools, such as simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
Working experience using LLMs for efficiency and quality.
Excellent knowledge of at least one scripting language, such as Python, Perl, or TCL.

Nice To Haves

Experience with power-aware (UPF) or similar verification methodology.
Experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR; this is a plus but not required.
Knowledge of formal verification methodology; this is a plus but not required.
Knowledge of emulation for verification technologies; this is a plus but not required.

Responsibilities

Establish verification methodology appropriate to the IP, with a scalable and portable environment.
Develop detailed test and coverage plans based on the microarchitecture.
Develop verification environments and components, including stimulus, checkers, assertions, trackers, and coverage.
Write tests and execute verification plans.
Bring up designs and DV environments and enable regression features.
Debug test failures.
Develop block-, IP-, and SoC-level testbenches.
Track and report DV progress using metrics including bugs and coverage.
Perform verification sign-off for RTL freeze and tape-out.
Use LLMs and related technologies to improve execution efficiency and quality.