Design Verification Engineer

Apple

19d

About The Position

At Apple, the Design Verification Engineer will help produce fully functional first silicon for IP designs. The role covers all phases of pre-silicon verification, including establishing design verification methodology, developing test plans and verification environments, writing tests, debugging, measuring coverage, and signing off for RTL freeze and tape-out. The engineer will ensure bug-free first silicon for part of an SoC or IP, develop detailed test and coverage plans based on microarchitecture, and create scalable, portable verification methodology and environments. Environment components include stimulus, checkers, assertions, trackers, and coverage. The role includes developing and executing verification plans; bringing up designs and verification environments; enabling regressions; debugging test failures; developing block-, IP-, and SoC-level testbenches; and tracking and reporting progress using metrics such as bugs and coverage. The engineer is also expected to use LLMs and related technologies to improve execution efficiency and quality.

Requirements

Bachelor of Science degree in a technical subject area.
At least 10 years of relevant industry experience.
Deep knowledge of object-oriented programming, SystemVerilog, and UVM.
Deep knowledge of developing scalable and portable testbenches.
Strong experience with verification methodologies and tools, including simulators, waveform viewers, build-and-run automation, coverage collection, and gate-level simulations.
Excellent knowledge of at least one scripting language, such as Python, Perl, or TCL.

Nice To Haves

Working experience using LLMs for efficiency and quality.
Experience with power-aware (UPF) or similar verification methodology.
Experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
Knowledge of formal verification methodology.
Knowledge of emulation for verification technologies.
A mindset focused on finding ways to break the design.

Responsibilities

Establish design verification methodology suitable for the IP, with a scalable and portable environment.
Develop detailed test and coverage plans based on microarchitecture.
Develop verification environments and components, including stimulus, checkers, assertions, trackers, and coverage.
Develop and execute verification plans for assigned features.
Perform design bring-up and verification-environment bring-up, enable regressions, and debug test failures.
Develop block-, IP-, and SoC-level testbenches.
Track and report design verification progress using metrics such as bugs and coverage.
Use LLMs and related technologies to improve execution efficiency and quality.
Complete pre-silicon verification activities, including test writing, debug, coverage, and sign-off for RTL freeze and tape-out.
Work toward bug-free first silicon for part of an SoC or IP.