Design Verification (DV) Engineer - 2027 Grads

Hudson River Trading•New York, NY

11d

About The Position

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technologies to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators. These high performance designs require even higher performance verification. We are looking for Design Verification (DV) engineers who are passionate about writing testbenches and building verification environments to exercise complex HDL. You are excited about exploring the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb. Design verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Requirements

Superb debugging and analytical skills
Experience with RTL functional verification
Proficiency in Python
Comfortable in a Linux environment
A bachelor’s degree in computer engineering, computer science or a related field

Nice To Haves

Familiarity with Cocotb preferred
C++ experience is a plus

Responsibilities

Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
Writing detailed verification plans
Quickly root-cause RTL bugs
Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
Managing test suites and continuous integration infrastructure
Developing and improving open-source and internal tools