Design Verification Engineer

Apple • Austin, TX

3d

About The Position

Apple Inc. is hiring a Design Verification Engineer in Austin, Texas. The role focuses on verifying system-on-chip (SoC) designs, including high-efficiency SoC architecture and standard SoC peripherals and subsystems. The engineer will develop coverage-driven verification plans, build reusable verification environments, and integrate verification components and suites across IP, subsystem, and SoC levels. The role works closely with design, architecture, software, firmware, external IP delivery teams, and verification methodology architects.

Requirements

• Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field.
• Experience and/or education using Verilog and VHDL to develop digital designs.
• Experience and/or education using SystemVerilog to develop test benches for digital designs, including reference models, stimulus generation, and design-under-test debugging.
• Experience and/or education writing programs and designing system models using object-oriented programming in C/C++.
• Experience and/or education with combinational and sequential circuit designs and their usage patterns to understand, verify, and debug digital designs.
• Experience and/or education understanding microprocessor architecture, processor organization, instruction set architecture, and assembly instructions for microprocessor design verification and integration.
• Experience and/or education understanding CPU architecture in relation to multithreading, interrupt handling, and semaphores, and how these features are used in SoCs.
• Experience and/or education using Linux/Unix operating systems to manage files, run commands, and monitor jobs.
• Experience and/or education using Perl, Bash, and Python to automate jobs and write programs that support verification flows.
• Experience and/or education using industry-standard Cadence and Synopsys simulators to design digital blocks, simulate test benches, and debug waveforms.

Responsibilities

• Understand high-efficiency SoC architecture, standard SoC peripherals, memory management schemes, low-power specifications, multiprocessor systems, and relevant interfaces and subsystems.
• Create coverage-driven verification plans from specifications, and review and refine plans to achieve coverage targets.
• Create IP-level module and subsystem verification plans, test benches, portable test benches, sequences, and test infrastructure.
• Architect reusable UVM-based test benches and integrate complex multi-instance VIPs, subsystem test benches, and test suites at the SoC level.
• Work with design, architecture, software, firmware, and external IP delivery teams to integrate and verify the overall SoC design.
• Collaborate with design verification methodology architects to improve verification flows.

What This Job Offers

• Job Type: Full-time