Design Verification Engineer

Apple • Waltham, MA

9d

About The Position

The Design Verification Engineer helps ensure bug-free first silicon for part of an SoC or IP design. The role covers all phases of pre-silicon verification, including establishing verification methodology, developing test plans and verification environments, writing tests, debugging, measuring coverage, and sign-off for RTL freeze and tape-out.

The engineer develops detailed test and coverage plans based on the micro-architecture and creates a scalable, portable verification environment with stimulus, checkers, assertions, trackers, and coverage. They bring up designs and verification environments, enable regressions, execute verification plans, debug test failures, and track and report progress using metrics such as bugs and coverage. The role also involves learning to develop block-, IP-, and SoC-level testbenches and using LLMs and related technologies to improve efficiency and quality.

Requirements

• Bachelor's degree in a technical subject area and at least 3 years of relevant industry experience, or equivalent.
• Strong knowledge of object-oriented programming, SystemVerilog, and UVM.
• Strong knowledge of developing scalable and portable testbenches.
• Proven experience with verification methodologies and tools, including simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
• Working experience using LLMs for efficiency and quality.
• Knowledge of a scripting language such as Python, Perl, or TCL.

Nice To Haves

• Master's degree in a technical subject area and relevant industry experience.
• Experience with power-aware (UPF) or similar verification methodology.
• Some experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
• Knowledge of formal verification methodology.

Responsibilities

• Establish verification methodology suitable for the IP and ensure the environment is scalable and portable.
• Develop detailed test and coverage plans based on the micro-architecture and features under responsibility.
• Develop verification environments, including stimulus, checkers, assertions, trackers, and coverage.
• Write tests, execute verification plans, and debug test failures.
• Perform design and DV environment bring-up and enable regressions.
• Support verification sign-off for RTL freeze and tape-out.
• Learn to develop block-, IP-, and SoC-level testbenches.
• Track and report DV progress using metrics including bugs and coverage.
• Use LLMs and related technologies to improve efficiency and quality.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level