Design Verification (DV) Engineer

DensityAI•Mountain View, CA

15h

About The Position

We're looking for an experienced Design Verification engineer with at least 5 years of pre-silicon verification experience in end-to-end verification for complex IP, subsystems, and/or SoC system level verification from plan to functional closure. This is a senior individual-contributor role and you'll partner closely with our HW-design and software teams, driving DensityAI's AI accelerator program from first silicon through scale-out.

Requirements

5+ years of experience in one or more of the following: Block Level/Sub System Verification, CPU Subsystem/IP integration, SoC/full-chip Verification, Emulation testing, DMA/NoC Verification, Multi-SoC/Die to Die protocol verification, Debug for functional closure of complex design or SOCs
Proven records on end-to-end pre-silicon verification ownership and deliverables
Strong Interest in optimizing Verification techniques and life cycle using the latest agentic/AI assisted flows
Exceptional abilities in analyzing and understanding specification from both hardware and software perspectives
Well-versed in UVM methodology and testbench architecture
Ability to define clear goals and milestones to meet aggressive timelines and quickly adapt to a dynamic design life cycle
Self driven and passionate, with a strong sense of respectful team collaboration
Flexible Mindset to jump in and contribute to multiple domains within verification as needed

Nice To Haves

RISC-V, formal verification, emulation platforms (Palladium, Veloce, or equivalent), or post-silicon bring-up

Responsibilities

Own an entire testing domain based on your expertise
Develop end-to-end testing strategy from IP to SOC-level and to emulation for our AI accelerator silicon
Use and develop AI-assisted tool flows to accelerate verification and emulation timeline