Design Verification Engineer

Apple • Cary, NC

12d

About The Position

At Apple, the Design Verification Engineer will help produce fully functional first silicon for IP designs and contribute to products used by millions of customers. The role covers all phases of pre-silicon verification, including establishing verification methodology, developing test plans and verification environments, writing tests, debugging, collecting coverage, and signing off for RTL freeze and tape-out. The engineer is responsible for verifying part of an SoC or IP and developing detailed test and coverage plans based on its micro-architecture.

The engineer will build scalable, portable verification environments and their components, including stimulus, checkers, assertions, trackers, and coverage. The work includes design and verification-environment bring-up, enabling regressions, debugging failures, tracking and reporting verification progress through metrics such as bugs and coverage, and developing block-, IP-, and SoC-level testbenches. The role also involves using LLMs and related technologies to improve verification efficiency and quality.

Requirements

• Bachelor's degree in a technical subject area and at least 10 years of relevant industry experience, or equivalent.
• Deep knowledge of object-oriented programming, SystemVerilog, and UVM.
• Deep knowledge of developing scalable and portable testbenches.
• Strong experience with verification methodologies and tools, including simulators, waveform viewers, build-and-run automation, coverage collection, and gate-level simulations.
• Working experience using LLMs to improve efficiency and quality.
• Experience with power-aware (UPF) or similar verification methodology.
• Excellent knowledge of at least one scripting language, such as Python, Perl, or TCL.

Nice To Haves

• Experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
• Knowledge of formal verification methodology.
• Knowledge of emulation technologies for verification.

Responsibilities

• Study design specifications and create test plans for assigned features.
• Establish verification methodology appropriate to the IP and develop scalable, portable verification environments.
• Develop SystemVerilog/UVM infrastructure and stimulus to stress the design.
• Develop testbench components including checkers, assertions, trackers, and coverage.
• Execute verification plans, including design bring-up and verification-environment bring-up.
• Write tests, enable regressions, debug test failures, fix failures, and close bugs.
• Track and report design-verification progress using metrics such as bugs and coverage.
• Support verification sign-off for RTL freeze and tape-out.
• Use LLMs and related technologies to improve verification efficiency and quality.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior