Design Verification Engineer

Apple • Cupertino, CA

3d

About The Position

Apple Inc. is hiring a Design Verification Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role is responsible for verifying complex digital IPs and collaborating with system architects and digital designers to clarify block-level specifications. The engineer uses specifications to create verification plans that cover functional, performance, stress, and error conditions, and owns verification test benches built with formal verification and UVM-based simulation.

The role develops SystemVerilog Assertions and constrained-random UVM test cases to achieve functional and code coverage. It also involves reviewing code for other chip blocks, developing precise specifications for digital control blocks, creating block- and chip-level verification plans and block-level verification elements, and helping architect chip- and system-level verification environments. The engineer develops drivers, tests, reference models, and checkers using SystemVerilog and UVM, debugs test failures with designers, and uses coverage to track progress and assess tape-out readiness. The position is 40 hours per week.

Requirements

• Master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field.
• Experience and/or education utilizing SystemVerilog to create block-level verification elements.
• Experience and/or education utilizing Verilog and VHDL to debug design issues and identify bug root causes.
• Experience and/or education utilizing digital hardware simulation to develop checkers and tests.
• Experience and/or education utilizing object-oriented programming and C to understand and debug firmware executions on chips.
• Experience and/or education utilizing Python, Perl, or algorithms to develop design verification automation flows.
• Experience and/or education utilizing chip simulations on CAD software, including debugging simulation failures for bug hunting.
• Finite State Machine design and verification experience to fully verify FSM designs.

Responsibilities

• Verify complex digital IPs.
• Work with system architects and digital designers to make block-level specifications clear and precise.
• Create verification plans that exercise functional, performance, stress, and error conditions in blocks.
• Own the creation of verification test benches using formal verification and UVM-based simulation.
• Build test cases using SystemVerilog Assertions and constrained-random UVM to achieve functional and code coverage.
• Participate in code reviews of other chip blocks and propose ways to help achieve bug-free designs on the first tape-out.
• Collaborate in developing precise design specifications for digital control blocks.
• Use design specifications to create block- and chip-level verification plans.
• Architect and create block-level verification elements.
• Assist in architecting chip- and system-level verification environments.
• Use SystemVerilog and UVM to develop drivers, tests, reference models, and checkers.
• Debug test failures and work with designers to develop fixes.
• Use functional and code coverage to track progress and gauge tape-out readiness.

Benefits

• Opportunity to participate in discretionary employee stock programs, including discretionary restricted stock unit awards.
• Ability to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain education expenses, including tuition, for formal education related to career advancement at Apple.
• May be eligible for discretionary bonuses or commission payments.
• May be eligible for relocation.

What This Job Offers

• Job Type: Full-time