Design Verification Engineer

Apple•Beaverton, OR

About The Position

At Apple, the Design Verification Engineer helps develop upcoming products by enabling fully functional first silicon for IP designs. The role covers all phases of pre-silicon verification, including establishing verification methodology, developing test plans and verification environments, writing tests, debugging, measuring coverage, and sign-off for RTL freeze and tape-out. The engineer is responsible for verification of part of the SoC or IP and for creating detailed test and coverage plans based on the micro-architecture. The position involves developing scalable, portable verification environments and their components, including stimulus, checkers, assertions, trackers, and coverage. The engineer develops and executes verification plans, supports design and DV-environment bring-up, enables regressions, debugs failures, and tracks and reports progress using metrics such as bugs and coverage. The role also involves using LLMs and related technologies to improve verification efficiency and quality, and learning to develop block-, IP-, and SoC-level testbenches.

Requirements

Bachelor’s degree in a technical subject area.
Minimum 3 years of relevant industry experience.
Strong knowledge of object-oriented programming, SystemVerilog, and UVM.
Strong knowledge of developing scalable and portable testbenches.
Proven experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
Working experience using LLMs for efficiency and quality.
Knowledge of a scripting language such as Python, Perl, or TCL.

Nice To Haves

A master’s degree in a technical subject area and relevant industry experience are strongly preferred.
Experience with power-aware (UPF) or similar verification methodology.
Some experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
Knowledge of formal verification methodology.

Responsibilities

Study design specifications and create test plans.
Establish verification methodology appropriate to the IP and develop scalable, portable verification environments.
Develop SystemVerilog/UVM infrastructure to stress the design.
Develop verification-environment components, including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans, including design and DV-environment bring-up and regression-enabling features.
Write tests, debug regression failures, and close bugs.
Develop block-, IP-, and SoC-level testbenches.
Track and report DV progress using metrics including bugs and coverage.
Complete verification sign-off for RTL freeze and tape-out.
Use LLMs and related technologies to improve verification efficiency and quality.