Design Verification Engineer

Apple•Cupertino, CA

4h•$150,400 - $225,300•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Review the design specifications, extracting attributes, and reviewing the test plan with verification, design and cross functional teams. Generate coverage databases and collaborating with design team to close the coverage. Develop regression scripts and running regressions on Apple‘s regression infrastructure. File tickets to track RTL bugs, providing designers with the waveform of the bug and the reproduction command. Develop test bench environment(s), directed and random/constrained tests to completely verify the design features. Develop functional coverage metrics to meet the verification goals. Develop reusable and scalable testbenches which can be easily integrated in higher level environments. Plan and develop checkers to identify design bugs.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.
Using SystemVerilog for constrained random test development
Using C for reference model and checker development.
Utilizing Perl, Python, or shell scripting for regression automation.
Applying Digital Electronics concepts to understand the design under test.
Utilizing simulators and waveform viewers, including VCS or Verdi, for running and debugging simulations.
Utilizing CPU architecture knowledge for verifying CPU based designs.
Using knowledge of Verilog RTL design constructs for debugging designs.
Using MATLAB to create models used in verification.

Responsibilities

Review the design specifications, extracting attributes, and reviewing the test plan with verification, design and cross functional teams.
Generate coverage databases and collaborating with design team to close the coverage.
Develop regression scripts and running regressions on Apple‘s regression infrastructure.
File tickets to track RTL bugs, providing designers with the waveform of the bug and the reproduction command.
Develop test bench environment(s), directed and random/constrained tests to completely verify the design features.
Develop functional coverage metrics to meet the verification goals.
Develop reusable and scalable testbenches which can be easily integrated in higher level environments.
Plan and develop checkers to identify design bugs.