Design Verification Engineer

Apple • Cupertino, CA

2d

About The Position

Apple Inc. is hiring a Design Verification Engineer in Cupertino, California, and various unanticipated locations throughout the United States. The role focuses on verifying chip designs against functional and performance goals through detailed specification review, test planning, simulation, regression analysis, and collaboration with design, micro-architecture, architecture, and software teams. The position is 40 hours per week.

The engineer will develop and refine verification methodologies and test benches, run and triage regressions, track issues, and assess coverage data. The role also involves developing reusable SystemVerilog test benches, applying OOP and UVM, automating regression workflows, using industry-standard simulation and waveform-debug tools, and designing algorithmic reference models.

The position requires a master's degree or foreign equivalent in Electrical Engineering or a related field, with relevant experience and/or education in the listed verification technologies and practices. The base pay range is $174,149–$225,300 per year, depending on skills, qualifications, experience, and location. Apple describes potential benefits including medical and dental coverage, retirement benefits, discounted products and services, tuition reimbursement for certain career-related education, employee stock programs, and possible discretionary bonuses or commission payments and relocation.

Requirements

• Master's degree or foreign equivalent in Electrical Engineering or a related field.
• Experience and/or education developing reusable SystemVerilog test benches with constraint-random and directed stimulus, monitors, checkers, and coverage points.
• Experience and/or education applying OOP principles, including encapsulation, abstraction, inheritance, and polymorphism, to build cycle-accurate and transaction-accurate behavior models.
• Experience and/or education implementing UVM verification environments.
• Experience and/or education producing verification and coverage plans and estimating verification effort.
• Experience and/or education automating regression workflows with Python, Ruby, or Perl.
• Experience and/or education executing simulations with industry-standard tools, including Cadence Xcelium.
• Experience and/or education analyzing simulation traces with waveform debuggers such as Verdi or Indago.
• Experience and/or education using UNIX/Linux command-line utilities.
• Experience and/or education designing and debugging algorithmic reference models.
• Experience and/or education collaborating across design, architecture, and software teams.

Responsibilities

• Review design and architecture specifications in detail to ensure alignment with functional and performance goals.
• Collaborate with design and micro-architecture teams to understand design requirements, constraints, and real-world use cases.
• Develop comprehensive test plans, test cases, and coverage plans to validate chip functionality and performance.
• Refine and design verification methodologies and test benches for improved efficiency and effectiveness.
• Run and triage regressions to identify and resolve chip design issues.
• Track issues and evaluate coverage data to ensure thorough testing and verification coverage.
• Collaborate with design, architecture, and software teams to understand use cases and corner conditions and develop effective test cases.
• Develop reusable SystemVerilog test benches with constraint-random and directed stimulus, monitors, checkers, and coverage points.
• Apply object-oriented programming principles to build cycle-accurate and transaction-accurate behavior models.
• Implement UVM to create scalable, modular, reusable verification environments aligned with project verification plans.
• Produce verification and coverage plans that estimate verification effort and align with project schedules and deliverables.
• Automate regression workflows using Python, Ruby, or Perl, including generating result charts and reusable verification components.
• Execute simulations using industry-standard tools, including Cadence Xcelium, to compile, run, and profile verification environments for RTL validation.
• Analyze simulation traces using waveform debuggers such as Verdi or Indago to identify design bugs and validate signal interactions.
• Use UNIX/Linux command-line utilities for file manipulation, data searching, and workflow automation.
• Design and debug algorithmic reference models to validate hardware functional correctness and performance characteristics.
• Integrate verification strategies with design and architecture requirements to support timely delivery of project milestones.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to advancing a career at Apple.
• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan.
• The role might be eligible for discretionary bonuses or commission payments.
• The role might be eligible for relocation.

What This Job Offers

• Job Type: Full-time