Design Verification Engineer

Apple • Cary, NC

8d

About The Position

The Design Verification Engineer will help deliver fully functional first silicon for IP designs by carrying out pre-silicon verification across the verification lifecycle. The work includes establishing verification methodology; developing test plans and verification environments; writing tests; debugging failures; tracking coverage; and signing off for RTL freeze and tape-out. The engineer will develop detailed test and coverage plans from micro-architecture and create scalable, portable verification environments with stimulus, checkers, assertions, trackers, and coverage. The role also involves bringing up designs and verification environments, enabling regressions, debugging test failures, tracking and reporting verification progress using metrics such as bugs and coverage, and using LLMs and related technologies to improve efficiency and quality. Verification spans block, IP, and SoC-level testbenches.

Requirements

• Bachelor’s degree in a technical subject area and at least 3 years of relevant industry experience, or equivalent.
• Strong knowledge of object-oriented programming, SystemVerilog, and UVM.
• Strong knowledge of developing scalable and portable testbenches.
• Proven experience with verification methodologies and tools, including simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
• Working experience using LLMs for efficiency and quality.
• Knowledge of a scripting language such as Python, Perl, or TCL.

Nice To Haves

• A master’s degree in a technical subject area and relevant industry experience is strongly preferred.
• Experience with power-aware (UPF) or similar verification methodology.
• Some experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
• Knowledge of formal verification methodology.

Responsibilities

• Study design specifications and create test plans.
• Establish verification methodology suitable for the IP and develop scalable, portable verification environments.
• Develop SystemVerilog/UVM infrastructure and stimulus to stress the design.
• Create verification environment components, including checkers, assertions, trackers, and coverage.
• Write tests and execute verification plans, including design and verification-environment bring-up.
• Enable regressions, debug test failures, fix failures, and close bugs.
• Develop detailed test and coverage plans based on the micro-architecture.
• Track and report design verification progress using metrics such as bugs and coverage.
• Complete verification sign-off for RTL freeze and tape-out.
• Use LLMs and related technologies to improve verification efficiency and quality.
• Develop block-, IP-, and SoC-level testbenches.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level