Design Verification Engineer - Compute

MatX•Mountain View, CA

4d•$160,000 - $600,000•Onsite

About The Position

MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. This role will contribute to MatX’s verification methodology with a scalable solution across blocks, subsystems, fullchip, and system-level validation. The engineer will own portions of verification execution at subsystem and chip-level, and create testbenches, tests, and related artifacts to achieve structural and functional coverage closure. They will also plan and drive intermediate and sign-off reviews on verification test plans, execution progress, and verification closure toward various silicon milestones including design freeze and tapeout.

Requirements

At least 5 years of silicon design-verification experience
End-to-end, concept-to-silicon tapeout experience — has driven verification from an architecture and/or design specification through design freeze and tapeout to production silicon
Production experience with conventional/advanced verification methodologies — SystemVerilog and UVM, assertion-based verification (ABV); comfort with both formal and simulated verification
Experience with Python, C/C++, and similar scripting and programming languages for verification and silicon modeling
Production experience creating portable tests and drivers that apply to silicon validation and post-silicon debug
Strong understanding of silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), memory management, and related functionalities

Nice To Haves

Numerics knowledge (floating-point / fixed-point arithmetic, rounding, precision)
Prior work on accelerators, DMA engines, or systolic operations / systolic arrays
Rust, or a functional-programming background — Haskell, or functionally-rooted HDLs such as Bluespec
Familiarity with emulation and prototyping platforms and methodologies
Hands-on experience with silicon debug and bring-up

Responsibilities

Contribute to MatX’s verification methodology with a scalable solution across blocks, subsystems, fullchip, and system-level validation
Own portions of verification execution at subsystem and chip-level, and create testbenches, tests, and related artifacts to achieve structural and functional coverage closure
Plan and drive intermediate and sign-off reviews on verification test plans, execution progress, and verification closure toward various silicon milestones including design freeze and tapeout