ASIC Design Verification Manager, TPU Compute
About The Position
As an ASIC Design Verification Manager for Google's TPU designs, you will lead a team and own functional verification for key components. You will guide the development of advanced verification infrastructure at the subchip, subsystem, and full-chip levels, including comprehensive test plans, diagnostic code, monitors, and checkers. You will collaborate closely with front-end design, architecture, performance, and power teams. By analyzing coverage across multiple dimensions, you will help ensure architectural compliance and functional correctness while driving the team toward performance and power goals. The role contributes to TPU technology supporting Google's AI/ML applications and requires verification expertise focused on TPU architecture and integration in AI/ML-driven systems. The AI and Infrastructure team delivers AI and infrastructure capabilities for Google customers, Googlers, and users worldwide, working across software and hardware, including TPUs, Google Cloud, networking, and data center operations.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with verification, SystemVerilog, and UVM.
- 3 years of experience in people management.
Nice To Haves
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- 12 years of experience with industry-standard tools, languages, and methodologies relevant to developing and verifying high-performance silicon.
- Experience leading verification efforts for complex SoC projects involving compute subsystems for AI/ML accelerators.
- Experience mentoring junior engineers and establishing verification quality standards, with strong investigative and communication skills.
- Proven record of managing SoC verification planning from architecture definition through silicon bring-up.
- Ability to influence cross-functional architecture, design, power, emulation, and software teams to optimize verification efficiency and product quality.
Responsibilities
- Lead the functional verification team for significant portions of the TPU Compute team, set and communicate individual and team priorities, provide regular feedback and coaching, and develop advanced verification infrastructure at subchip, subsystem, and full-chip levels.
- Define and drive comprehensive verification strategies for complex compute subsystems, collaborating with design, architecture, and power teams to achieve architectural compliance and align with performance and power goals.
- Architect scalable, reusable verification environments and flows, and drive adoption of industry-leading methodologies to improve team efficiency.
- Provide technical leadership and mentorship to junior engineers, conduct code reviews, establish verification quality standards, and guide cross-functional efforts for silicon bring-up.
- Partner with architects and design leads to influence micro-architectural decisions that improve verification throughput and overall quality.
Benefits
- 20% bonus target
- Equity
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Manager
