ASIC Power Design Engineer II (Full Time) - United States

Cisco•San Jose, CA

About The Position

The Silicon One team develops hardware platforms for Cisco’s Switching, Routing, and Wireless products. The team covers full product development, from design through qualification and production, and works across silicon, optics, and hardware platforms. The ASIC Power Design Engineer II implements and optimizes low-power design methods and performs block- and full-chip power analysis across operating modes, process-voltage-temperature corners, and functional activity scenarios. The role works closely with RTL design and architecture teams to identify power bottlenecks and guide RTL and microarchitectural improvements. It also supports timing closure, signal integrity, and power targets on advanced process nodes; automates design and analysis workflows; and participates in post-silicon power and performance validation and correlation with pre-silicon models. This posting advertises potential opportunities; the exact role may not be open at the time of application. Cisco may contact applicants if a relevant position opens. Applications are accepted until further notice.

Requirements

Within the past 3 years, completed—or currently enrolled with expected completion within 12 months—in a Bachelor's program and have 2 years of relevant experience, or completed a Master's degree program with 0 years of relevant experience. Relevant fields include ASIC Design or Power Design.
Strong familiarity with low-power design concepts and techniques, including UPF/IEEE 1801, clock gating, multi-voltage domains, power switches, retention cells, and leakage-versus-dynamic-power trade-offs.
Proficiency with hardware description languages such as SystemVerilog or Verilog.
Scripting capability in TCL, Python, or Perl for EDA tool automation and data parsing.
Familiarity with a Linux/Unix development environment.

Nice To Haves

Direct experience running activity-driven power analysis using FSDB, VCD, or SAIF waveforms generated from gate-level and RTL simulations.
Experience with industry-standard EDA tools, including synthesis and place-and-route tools such as Synopsys Design Compiler, Fusion Compiler, IC Validator, or Cadence Innovus, and timing and signoff tools such as Synopsys PrimeTime/PrimeTime-SI, PrimePower, StarRC, or Siemens Calibre.
Experience with power integrity, IR-drop, or EM analysis tools such as Ansys RedHawk or Voltus.
Understanding of sophisticated FinFET/GAA process-node design rules and low-power library architectures.
Excellent problem-solving, partnership, and communication skills within multifunctional teams.

Responsibilities

Implement and optimize low-power design methodologies, including clock gating, power gating, multi-Vt, dynamic voltage and frequency scaling, and UPF/CPF power intent.
Perform block- and full-chip power analysis and estimation using Synopsys PrimePower (PTPX) across operating modes, PVT corners, and functional activity scenarios using VCD, FSDB, or SAIF.
Collaborate with RTL design and architecture teams to identify power bottlenecks and guide RTL and microarchitectural power optimizations.
Achieve timing closure, signal integrity, and power targets across advanced FinFET and GAA process nodes.
Develop and maintain automated design and analysis workflows using Python, TCL, and Perl.
Participate in post-silicon power and performance validation and correlate results against pre-silicon PrimePower models.

Benefits

Medical, dental, and vision insurance.
401(k) plan with a Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Paid holidays and a floating holiday for non-exempt employees.
Paid birthday day off, year-end holiday shutdown, and paid personal wellness days.
Paid vacation time for non-exempt employees; exempt employees participate in a flexible vacation time-off program with no defined limit, subject to availability and business limitations.
Sick time off, including carryover of unused sick time subject to the stated limit.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Annual bonuses for eligible non-sales employees, subject to Cisco policies.
Employees may be eligible for Cisco restricted stock unit grants, subject to continued employment and vesting terms.