ASIC Design Verification Engineer II Full Time - United States
About The Position
The ASIC Design Verification Engineer II will help develop Cisco data center solutions by verifying ASICs in simulation, emulation, and during ASIC bring-up. The role collaborates with verification engineers, designers, hardware teams, and other cross-functional partners to support seamless integration and performance of Cisco hardware platforms. Responsibilities include maintaining and improving design verification environments, building test benches for new blocks, creating verification plans and tests, debugging regression failures, and driving modules to verification closure. The engineer will also implement and review code and functional coverage to support complete verification coverage. This posting advertises potential job opportunities; the exact role may not be open currently. Applications are accepted until further notice. Minimum qualifications must have been completed within the past three years or be expected within the next 12 months.
Requirements
- Meet one of the following education and experience combinations, completed within the past three years or expected within the next 12 months: a master's degree with zero years of work experience, or a bachelor's degree with two years of work experience.
- Qualifying education and work experience must be in ASIC Engineering, Verification, or a related field.
- Experience with SystemVerilog and UVM methodology.
- Experience with scripting using Perl and/or Python.
Nice To Haves
- Experience using UVM and SystemVerilog for ASIC verification, including verification of complex ASIC blocks and/or clusters.
- Experience with functional coverage and constrained-random design verification environments.
- Experience verifying complex blocks, clusters, and SoC top levels.
- Experience with Veloce/HAPS.
- Experience building test benches from scratch, including SystemVerilog constraints, structures, and classes.
- Effective verbal and written communication skills.
Responsibilities
- Maintain and enhance existing design verification environments.
- Construct test benches for new blocks, including scoreboards, agents, sequencers, and monitors.
- Write test plans and develop test cases.
- Debug regression failures and drive modules to verification closure.
- Ensure complete verification coverage through implementation and review of code and functional coverage.
- Collaborate with verification engineers, designers, hardware teams, and other cross-functional teams to verify ASICs in simulation, emulation, and during ASIC bring-up.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Cisco restricted stock unit grants may be available, subject to eligibility and vesting conditions
- 10 paid holidays per full calendar year
- One floating holiday for non-exempt employees
- One paid day off for employee's birthday
- Paid year-end holiday shutdown
- Four paid personal wellness days
- Non-exempt employees receive 16 days of paid vacation per full calendar year, accrued at 4.92 hours per pay period for full-time employees
- Exempt employees participate in a flexible vacation time-off program with no defined limit, subject to availability and business limitations
- 80 hours of sick time provided on the hire date and each January 1 thereafter, with up to 80 unused hours carried forward
- Additional paid time away may be requested for critical or emergency family issues
- Optional 10 paid volunteer days per full calendar year
- Non-sales employees may be eligible for annual bonuses, subject to Cisco policies
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
