ASIC DFT Engineer I (Full Time) - United States

Cisco•San Jose, CA

About The Position

The ASIC DFT Engineer I will work in Cisco’s Silicon One development organization, focusing on design-for-test for ASICs. The role works with frontend RTL and backend Physical Design teams to understand chip architecture and establish DFT requirements early in the design cycle. The engineer implements hardware DFT features for ATE, in-system test, debug, and diagnostics; develops automation scripts; and collaborates with Design, Design Verification, and Physical Design teams to integrate and validate test logic throughout implementation and post-silicon validation. The role also supports test timing and logic-equivalency validation using SystemVerilog and uses ATPG and EDA tools for test-pattern generation and analysis.

Requirements

Bachelor’s degree completed within the past three years or expected within the next 12 months, in ASIC DFT or a related field.
Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST, including memory BIST and boundary scan.
Familiarity or introductory hands-on exposure to EDA and ATPG tools, with scripting or coding skills in Python, Tcl, or Perl.
Experience working with gate-level simulations and debugging using simulators such as VCS.

Nice To Haves

Practical experience or strong coursework in verification, including SystemVerilog, logic equivalency checking, and test-timing validation.
Understanding of basic VLSI circuit physical behaviors in silicon, such as electromigration and temperature/voltage variation effects, and familiarity with basic timing concepts such as setup/hold times and metastability.
Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis.
Strong verbal and written communication skills for collaborating with frontend RTL, backend Physical Design, and verification teams.

Responsibilities

Implement hardware DFT features supporting ATE, in-system test, debug, and diagnostics.
Create and enhance automation scripts to improve implementation robustness and efficiency.
Work with Design, Design Verification, and Physical Design teams to integrate and validate test logic throughout implementation and post-silicon validation flows.
Collaborate with team members to validate test timing and logic equivalency using SystemVerilog.
Use ATPG and EDA tools, including TestMax, Tetramax, Tessent, and PrimeTime, for test-pattern generation and analysis.

Benefits

Medical, dental, and vision insurance, subject to plan eligibility rules.
401(k) plan with Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Potential Cisco restricted stock unit grants, subject to eligibility and continued employment.
Paid holidays and a floating holiday for non-exempt employees.
Paid birthday day off, year-end holiday shutdown, and personal wellness days.
Paid vacation or flexible vacation time off, depending on employee classification.
Paid sick time.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Annual bonus eligibility for non-sales roles, subject to Cisco policies.