ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid)

Cisco•San Jose, CA

6d•Hybrid

About The Position

Cisco Silicon One is seeking a Signal and Power Integrity Engineer to help develop next-generation ASIC packaging for use across Cisco platforms. The role defines, designs, and verifies ASIC packaging, and develops, documents, and implements design rules for ultra-high-speed signaling while ensuring product power, performance, and area goals are met. The engineer analyzes substrate signal and power integrity, works with layout teams to optimize solutions across interposer, substrate, and PCB, and develops ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. The role also collaborates with system partners, vendors, and design leads to achieve combined power and signal integrity and resolve complex technical issues using advanced technology design rules. The position requires living within commuting distance of Cisco’s San Jose, California office and commuting there at least 4–5 days per week.

Requirements

Bachelor’s degree in Electrical Engineering and at least 4 years of relevant signal and power integrity experience; or a Master’s degree in Electrical Engineering and at least 2 years of relevant experience; or a PhD in Electrical Engineering and at least 0 years of related experience; or equivalent related work experience.
Experience with high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Experience with pre- and post-layout SI/PI simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and mitigate crosstalk.
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
Must live within commuting distance of the San Jose, California office and commute to the office at least 4–5 days per week.

Nice To Haves

Experience articulating ideas and technical concepts to diverse audiences, verbally and in writing.
Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
Experience with die-to-die interfaces such as UCIe or proprietary interfaces.
Experience with advanced packaging such as CoWoS, EMIB, or interposer-based designs, including SI/PI analysis of 2.5D ASIC packaging.
Experience with Vector Network Analysis.
Experience with IBIS.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling while ensuring product power, performance, and area goals are met.
Analyze substrate signal integrity (SI) and power integrity (PI), and provide feedback to the layout team to develop optimal solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity.
Resolve complex technical issues using advanced technology design rules.

Benefits

Medical insurance
Dental insurance
Vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Paid holidays and a floating holiday for non-exempt employees
Paid day off for employee’s birthday
Paid year-end holiday shutdown
Paid personal wellness days
Flexible vacation time off for eligible exempt employees
Paid vacation time for non-exempt employees
Sick time off
Additional paid time away may be requested for critical or emergency family issues
Optional paid volunteer days
Annual bonuses may be available for non-sales roles
Employees may be eligible for Cisco restricted stock unit grants