ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid)

Cisco•San Jose, CA

7d•$155,000 - $222,600•Hybrid

About The Position

Cisco Silicon One is seeking a Signal and Power Integrity Engineer to help develop next-generation ASIC packaging for deployment across Cisco platforms. The role involves defining, designing, and verifying ASIC packages, developing rules for ultra-high-speed signaling, and analyzing substrate signal and power integrity. The engineer will collaborate with layout teams, system partners, vendors, and design leads to optimize solutions across interposers, substrates, and PCBs, and to resolve complex technical issues. The position is based near Cisco’s San Jose, California office and requires commuting to the office at least 4–5 days per week.

Requirements

Bachelor’s degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience; or a Master’s degree in Electrical Engineering and 2+ years of relevant experience; or a PhD in Electrical Engineering and 0+ years of related experience; or equivalent related work experience.
Experience with high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Experience with pre- and post-layout SI/PI simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and mitigate crosstalk.
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
Must live within commuting distance of the San Jose, California office and commute there at least 4–5 days per week.

Nice To Haves

Ability to articulate ideas and technical concepts to diverse audiences, verbally and in writing.
Experience with high-bandwidth memory (HBM) or high-speed memory interface signal integrity.
Experience with die-to-die interfaces, such as UCIe or proprietary interfaces.
Experience with advanced packaging such as CoWoS, EMIB, or interposer-based designs, including SI/PI analysis of 2.5D ASIC packaging.
Experience with Vector Network Analysis.
Experience with IBIS.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling while meeting product power, performance, and area goals.
Analyze substrate signal integrity and power integrity, and collaborate with layout teams to develop solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve power and signal integrity goals and resolve complex technical issues using advanced technology design rules.

Benefits

Medical, dental, and vision insurance.
401(k) plan with Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Cisco restricted stock unit grants may be available, subject to eligibility and continued-employment vesting conditions.
10 paid holidays per full calendar year and, for non-exempt employees, one floating holiday.
Paid birthday day off, year-end holiday shutdown, and four paid personal wellness days.
Non-exempt employees receive 16 days of paid vacation per full calendar year, accrued at 4.92 hours per pay period for full-time employees.
Exempt employees participate in a flexible vacation time-off program with no defined usage limit, subject to availability and business limitations.
80 hours of sick time provided on hire and each January 1, with up to 80 unused hours carried forward.
Additional paid time away may be requested for critical or emergency family issues.
Optional 10 paid volunteer days per full calendar year.
For non-sales roles, eligibility to earn annual bonuses, subject to Cisco policies.