Signal and Power Integrity Engineer

Microsoft • Redmond, WA

5d • $102,100 - $219,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s Intelligent Cloud mission by delivering infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. The Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages computer chips, including Azure Cobalt. The Silicon Manufacturing and Product Engineering (SMPE) team supports the quality, delivery, scale, planning, and sustainability of Microsoft cloud hardware.

Microsoft is seeking a Senior Signal and Power Integrity Engineer to develop advanced power delivery and signaling solutions for High Performance Computing (HPC) silicon designs. The engineer will drive completion of signal and power integrity (SIPI) design solutions that support system-on-chip (SoC) performance and coordinate across silicon, packaging, and system design teams. The role spans end-to-end power delivery and signal integrity design from silicon through package, platform, system, and cloud, including solutions for compute and AI SoCs and platforms, chiplet architectures, advanced packaging, and advanced silicon nodes.

The position involves designing, modeling, and simulating signal and power integrity for data center processors and their platforms. This includes DC, AC, and transient power-delivery simulations, as well as link and electrical simulations to assess I/O performance. The engineer collaborates with architects and engineers across silicon, platforms, motherboards, packages, thermal, power, and performance, and drives architecture and system-design decisions across product lines and stakeholder groups.

Applicants must meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check upon hire or transfer and every two years thereafter. The role also requires access to export-controlled information. Candidates must provide qualifying citizenship, U.S. residency, or other protected-status documentation, with citizenship verified using a valid passport where applicable.

The role is listed as Silicon Engineering IC3. The typical U.S. base pay range is $102,100–$202,200 per year; a different range applies in the San Francisco Bay area and New York City metropolitan area, where the range is $133,800–$219,200 per year. Certain roles may be eligible for benefits and other compensation. The position will remain open for at least five days, with applications accepted on an ongoing basis until filled.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or bachelor's degree in one of these fields and at least 2 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Ability to provide documentation establishing eligibility to access export-controlled information, such as proof of citizenship, U.S. residency, or other protected status; citizenship is verified with a valid passport where applicable.

Nice To Haves

• Expertise in signal and power integrity and delivery, system design, and IP design, with knowledge of product development and at least 5 years of design and electrical modeling experience.
• Working knowledge of end-to-end system SIPI design and architecture.
• Industry knowledge of technology trends and the landscape across silicon IP, advanced packaging, substrate technology, board technology, and platform design.
• Written and verbal communication, teamwork, negotiation, and presentation skills.
• At least 5 years of experience in silicon packaging product development.
• Experience with high-speed signal design and/or power integrity modeling for HPC products.
• Experience with foundry silicon, OSAT, and substrate technologies.

Responsibilities

• Implement end-to-end power delivery and signal integrity design strategies for compute and AI SoCs and platforms, spanning silicon, package, platform, system, and cloud.
• Deliver SIPI solutions that meet HPC demands across the entire system.
• Drive future power and signal integrity solutions for chiplet architectures using advanced packaging and advanced silicon nodes.
• Design, model, and simulate signal and power integrity for data center processors and platforms, including IP design, voltage regulators, motherboards, CPU packages, silicon, and decoupling capacitor solutions.
• Perform DC, AC, and transient simulations to characterize noise and impedance across the power delivery path, and perform link and electrical simulations to validate I/O performance from platform to silicon.
• Collaborate with silicon and platform architects, motherboard and package designers, thermal architects and engineers, and power and performance engineers.
• Drive execution of architecture solutions across product lines or product groups, applying cross-functional expertise, industry practices, and lessons learned while accounting for design trends and future concepts.
• Drive engineering system-design decisions in collaboration with internal and external stakeholders, accounting for platform-specific technology decisions and developing system models based on current and anticipated design needs and trade-offs.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior