Chip Package Signal and Power Integrity Engineer

Google•Sunnyvale, CA

1d•$163,000 - $236,000

About The Position

As a Signal Integrity/Power Integrity Engineer, you will lead chip and package design to ensure optimal signal integrity and power integrity performance and system co-design from concept through production. You will collaborate with teams across chip design, IP, system design, software, and external vendors to drive signal and power design implementations on chip and advanced packages. The role supports Google TPU technology for AI/ML hardware acceleration and contributes to the design and integration of custom silicon solutions.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
7 years of experience with SI/PI design for chip/package or system PCB.
Experience with industry Signal Integrity and Power Integrity (SIPI) modeling tool chains such as HFSS, ADS, Sigrity, or Siwave.

Nice To Haves

Master’s degree or PhD in Electrical Engineering or SI/PI.
Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, and expertise in SI/PI analysis for high-speed interconnects.
Knowledge of next-generation memory and chiplet standards, including timing budgets, design, and sign-off methodologies.
Understanding of Static Timing Analysis, on-chip DVD/EMIR, system voltage budgets, and voltage regulator modeling and design.
Proficiency in Python, Matlab, or C++ for establishing automation flows and advanced data processing and analysis.
Ability to lead cross-functionally across chip design, physical design, STA, packaging, system, and validation teams.

Responsibilities

Lead SI/PI analysis for High-Performance Computing using 2.5D/3D package technologies to define specifications and optimize chip floorplans, power trees, and netlists.
Drive next-generation memory interface development and evaluate high-speed interface IPs, balancing trade-offs across IO PHY, SI/PI, and physical design.
Own post-silicon validation and qualification of high-speed interfaces to support successful New Product Introduction (NPI).
Partner with chip and system design teams, suppliers, and vendors to establish SI/PI goals, define design boundaries, and manage DFM trade-offs.
Provide feedback on chip floorplans to maximize package and system routability and SI/PI, and develop methodologies to improve simulation accuracy and productivity.