Signal Integrity & Power Integrity Engineer - Los Altos

Majestic Labs•Los Altos, CA

11h

About The Position

Majestic Labs is a fast-moving US-Israeli AI startup building custom AI servers for demanding inference and training workloads. The company is seeking a Senior Signal Integrity (SI) and Power Integrity (PI) Engineer to own end-to-end electrical link performance across high-speed interconnects, from architecture and pre-silicon modeling through silicon bring-up, validation, and high-volume manufacturing. This is a hands-on technical role for an engineer with experience taking multiple products from concept to production and addressing issues that arise in volume manufacturing.

Requirements

10+ years of hands-on SI/PI engineering experience in the semiconductor, systems, or networking hardware industry.
Demonstrated experience across the full product lifecycle, from architecture through production and sustained high-volume manufacturing; simulation-only experience is not sufficient.
Deep working knowledge of high-speed SerDes signaling, including 224G or comparable leading-edge electrical interfaces, and PCIe link architecture.
Solid experience with parallel/source-synchronous interfaces such as DDR/memory buses and chip-to-chip interconnects.
Proficiency with COM-based analysis and IBIS-AMI modeling for channel compliance and margin assessment.
Strong command of industry-standard tools: Ansys HFSS, Ansys PowerSI or equivalent 2.5D/3D field solvers, Keysight ADS, and MATLAB.
Hands-on proficiency with SI/PI lab testing and validation equipment, including VNAs for S-parameter extraction, TDR/TDT for impedance and discontinuity characterization, and oscilloscopes for eye diagram, jitter, and signal quality measurement.
Familiarity with power integrity fundamentals, including PDN impedance analysis, decoupling strategy, DC/AC drop, and chip-package-board co-design.
Experience working with cross-functional teams, including ASIC design, package engineering, PCB layout, test/ATE, and manufacturing, to drive designs to closure.
Excellent written and verbal communication skills, with the ability to clearly present technical risks and trade-offs to engineering and program stakeholders.

Nice To Haves

Experience with additional high-speed standards such as CXL and Ethernet SerDes.
Scripting or automation experience with Python for simulation flow automation or data analysis.
Experience with connector, cable, or optical module electrical characterization.
Familiarity with signal/power co-simulation and chip-package-system (CPS) modeling flows.
Exposure to compliance testing and industry standards bodies such as PCI-SIG, OIF-CEI, and JEDEC.

Responsibilities

Own signal integrity and power integrity analysis for end-to-end high-speed links, including package, connector, PCB, and cable interconnects.
Drive SI/PI closure for high-speed SerDes interfaces (112G/224G-class), PCIe (Gen5/Gen6+), and parallel or single-ended interfaces such as DDR/LPDDR memory and chip-to-chip links.
Perform pre-silicon channel modeling, budgeting, and margin analysis using COM, IBIS-AMI, and statistical eye methodologies.
Build and correlate 3D/2.5D EM models using HFSS and PowerSI against lab measurements using VNA, TDR, BERT, and oscilloscopes to validate channel and package performance.
Perform system-level PDN analysis, develop decoupling strategies, and conduct power/SI co-design across chip, package, and board.
Use ADS and MATLAB for circuit-level simulation, link budget analysis, and custom post-processing or automation of simulation and lab data.
Support silicon bring-up, debugging, and characterization in the lab; identify root causes of SI/PI-related failures and drive corrective actions.
Partner with ASIC, package, PCB layout, and mechanical teams to define design rules, stackups, routing guidelines, and connector and material selection.
Lead products through DVT/PVT and into high-volume manufacturing, including establishing test limits, correlating ATE/system-level test data to simulation, and resolving field or yield issues related to SI/PI margin.
Contribute to internal methodology, tooling, and design guideline development.