Power Delivery & Integrity Engineer - Los Altos

Majestic Labs • Los Altos, CA

19h

About The Position

Majestic Labs is seeking a highly skilled Senior Power Engineer to lead the definition of board-level and rack-level power delivery architecture for next-generation, multi-kilowatt AI server platforms. The role owns end-to-end design of high-current power delivery paths to advanced SoCs, including voltage conversion and regulator strategy, Power Delivery Network (PDN) design and decoupling schemes, and design tradeoffs to maximize efficiency, optimize thermal performance, and ensure system performance while considering OCP/Open Rack power distribution standards. The engineer will work cross-functionally with silicon, mechanical, thermal, and systems teams to deliver robust, efficient, and scalable power delivery.

Majestic Labs is a fast-moving US-Israeli AI startup building custom AI servers for large-scale inference and training. It is backed by investors and led by industry veterans. The company seeks collaborative, forward-thinking engineers and operators who tackle complex challenges from first principles.

Requirements

• BS or MS in Electrical Engineering or a related field.
• 10+ years of experience in high-power delivery design.
• Demonstrated experience designing high-current, low-voltage power delivery for SoCs.
• Deep expertise in power integrity, PDN modeling, VRM design, target impedance definition, and transient response optimization.
• Proficiency with SPICE, PDN simulation tools such as Keysight, Cadence Sigrity/Clarity, or Ansys SIwave, and measurement equipment such as VNAs, oscilloscopes, and electronic loads.
• Solid understanding of package-to-PCB PDN interactions.
• Strong communication and cross-functional collaboration skills.

Nice To Haves

• Familiarity with EMI/EMC mitigation in high-current environments.
• Experience in server-class PCB design, including stackup planning, high-current routing, and decoupling strategies.
• Background in thermal-mechanical co-design for high-power modules.
• Knowledge of rack-level power architectures, ORv3/OCP standards, power shelves, and busbar systems.

Responsibilities

• Architect and design board-level, server-level, and rack-level power delivery systems for high-power subsystems.
• Define PDN topology, including VRMs, POLs, vertical and lateral power routing, and high-current interfaces.
• Select components, including VRMs, FETs, inductors, bulk capacitors, MLCCs, connectors, and busbars; develop derating, margin, and reliability guidelines.
• Lead decoupling capacitor strategy across package and PCB layers to meet target impedance and transient response goals.
• Drive power integrity analysis, including AC/DC, Z-target, transient, and EMI/EMC analysis, and validate designs through modeling, simulation, and laboratory measurement.
• Collaborate with mechanical and thermal teams to align high-current routing, cooling requirements, and system constraints.
• Partner with silicon and package engineering to co-design vertical PDN paths, including socket interfaces, pin/bump maps, and transient load profiles; review and advise silicon design to improve power integrity.
• Develop test plans for PDN validation, transient load tests, impedance measurement, and system bring-up.
• Provide expertise during failure analysis, root-cause investigations, and corrective actions for system power issues.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior