Signal Integrity Engineer

Pure Storage•Santa Clara, CA

2d•Onsite

About The Position

As a Signal Integrity Engineer at Everpure, you will support the development and validation of high-performance storage platforms to ensure robust electrical performance. Working with experienced design engineers, you will contribute to electrical modeling, design reviews, lab testing, and issue resolution across the product lifecycle. You will build hands-on SI expertise while collaborating with Hardware Design, PCB Layout, firmware, and manufacturing teams. The role supports high-speed interfaces across hardware products, from initial link budgets through production release, and includes technical work on design standards, system-level debugging, and engineering automation. The position is expected to work primarily from Everpure’s Santa Clara, California office, subject to company policies and approved leave or travel.

Requirements

Foundational knowledge of high-speed channel design and validation for modern interfaces such as PCIe Gen4+, 25G+ SerDes Ethernet, and DDR4/DDR5.
Understanding of electromagnetic concepts, crosstalk mitigation, and jitter analysis.
Exposure to industry-standard EDA tools such as HyperLynx, Sigrity, Simbeor, or HFSS for pre- and post-layout signal-integrity analysis, including IBIS-AMI, COM, and channel modeling.
Hands-on laboratory experience using high-speed instruments such as a VNA, TDR, BERT, or oscilloscopes.
Ability to work effectively on a cross-functional team, communicate clearly, ask questions, document results, learn from senior engineers, and contribute to technical decisions.
Experience with scripting or data analysis, preferably using Python, MATLAB, or similar tools, to automate analysis, process results, or generate reports.

Responsibilities

Support signal integrity for hardware products and high-speed interfaces such as PCIe Gen5+, 800G Ethernet, and DDR5, helping ensure reliability and maximize performance margins from initial link budgets through production release.
Collaborate with PCB layout, hardware, and mechanical teams to define design standards for stackups, materials, routing rules, and constraints, with the goals of first-pass success and manufacturing quality across product lines.
Serve as the SI technical anchor for complex system-level debugging, root-cause analysis, and corrective action across prototypes, validation, and field escalations.
Develop and standardize automated simulation flows, reporting pipelines, and continuous-integration-style checks for model and layout quality across the hardware organization.
Contribute to electrical modeling, design reviews, and laboratory testing throughout the product lifecycle.
Work cross-functionally with Hardware Design, PCB Layout, firmware, and manufacturing teams.