Principal Signal Integrity Engineer
About The Position
Hewlett Packard Enterprise is seeking a Principal Signal Integrity Engineer to join an experienced signal integrity team working on cutting-edge networking product design. The team performs high-speed ASIC PAM4 SerDes and system-level signal and power integrity analysis, with expertise spanning channel analysis, clocking, I/O timing, on-die and system-level power integrity, CPM modeling, PDN optimization, and PCB design for signal and power integrity. The role is designated onsite, with the expectation that the employee will primarily work from an HPE office. The position requires extensive signal integrity analysis experience and hands-on work with high-speed ASIC PAM4 SerDes technologies. The expected base salary in California is USD 181,000–367,000 annually; variable incentives may also be offered. Actual offers may vary based on geographic location, experience, education, training, and skill level.
Requirements
- Typically, 10 or more years of signal integrity analysis experience with a bachelor's degree in Electrical Engineering, Computer Engineering, Microwave Engineering, and/or RF Engineering.
- Typically, 8 or more years of signal integrity analysis experience with a master's degree in Electrical Engineering, Computer Engineering, Microwave Engineering, and/or RF Engineering.
- Experience with 56G/112G ASIC PAM4 SerDes technologies.
- Hands-on experience with serial channels up to 200G line rates for coefficient tuning and TP1A measurements.
- Good oral and written communication skills.
- Ability to collaborate with people across geographies and within a matrix organization.
- Ability to work on several projects simultaneously.
Nice To Haves
- 200G ASIC PAM4 experience.
- Proficiency with CAD tools such as Ansys HFSS, SIwave, ADS, Allegro, Sigrity, and MATLAB.
- Proficiency with lab equipment such as oscilloscopes, Vector Network Analyzers, Time Domain Reflectometers, Spectrum Analyzers, and phase noise analyzers.
- Good lab debugging skills.
- Strong capabilities in debugging and providing solutions for ASIC PAM4 SerDes and channel performance issues.
- Experience implementing system clocks and a solid understanding of PLL design and debugging.
- Experience with PCB stack-up design using 2-D field solvers.
Responsibilities
- Perform channel operating margin (COM) analysis and provide design trade-offs among ASIC packages, boards, and connectors.
- Develop ASIC PAM4 SerDes channel simulation models and correlate them with test structures.
- Correlate ASIC PAM4 SerDes simulation results with measurements and work with component and ASIC vendors to improve model accuracy.
- Perform PCB timing analysis and work with board engineers and layout designers to implement signal integrity design rules.
- Develop and document layout and signal integrity design rules and checklists.
- Tune ASIC PAM4 SerDes parameters to improve serial-link design margins.
- Perform signal integrity DVT measurements on boards and correlate simulations with DVT measurements.
- Provide technical assessments of projects to the signal integrity management team.
Benefits
- Comprehensive benefits supporting physical, financial, and emotional wellbeing.
- Programs supporting career development and professional growth.
- Variable incentives may also be offered.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Principal
