Principal Signal Integrity Engineer
About The Position
Hewlett Packard Enterprise is hiring a Principal Signal Integrity Engineer to work onsite at an HPE office as part of an experienced signal integrity team. The team performs high-speed ASIC PAM4 SerDes and system-level signal and power integrity analysis for networking products. Its areas of expertise include high-speed ASIC PAM4 SerDes, channel analysis, clocking, I/O timing, on-die and system-level power integrity, CPM modeling, PDN optimization, and PCB design for signal and power integrity. The role focuses on analyzing and improving high-speed serial links and networking system designs, including simulation and measurement correlation, PCB timing and layout rules, and technical project assessment. The position requires experience with 56G/112G ASIC PAM4 SerDes; 200G ASIC PAM4 experience is desired. The listed annual base salary range for California is USD 181,000–367,000. Actual offers may vary based on location, experience, education or training, and skill level; variable incentives may also be offered.
Requirements
- Typically, 10 or more years of signal integrity analysis experience with a bachelor's degree in Electrical Engineering, Computer Engineering, Microwave Engineering, and/or RF Engineering.
- Typically, 8 or more years of signal integrity analysis experience with a master's degree in Electrical Engineering, Computer Engineering, Microwave Engineering, and/or RF Engineering.
- Experience with 56G/112G ASIC PAM4 SerDes technologies.
- Hands-on experience with serial channels up to 200G line rates for coefficient tuning and TP1A measurements.
- Good oral and written communication skills.
- Ability to collaborate across geographies and in a matrix organization.
- Ability to work on several projects simultaneously.
Nice To Haves
- Experience with 200G ASIC PAM4.
- Proficiency with CAD tools such as Ansys HFSS, SIwave, ADS, Allegro, Sigrity, and MATLAB.
- Proficiency with laboratory equipment such as oscilloscopes, Vector Network Analyzers, Time Domain Reflectometers, Spectrum Analyzers, and phase noise analyzers.
- Good laboratory debugging skills.
- Strong capabilities in debugging and providing solutions for ASIC PAM4 SerDes and channel performance issues.
- Experience with system clock design implementation and a solid understanding of PLL design and debugging.
- PCB stack-up design using 2-D field solvers.
Responsibilities
- Perform COM (channel margin analysis) to evaluate design trade-offs among ASIC packages, boards, and connectors.
- Develop ASIC PAM4 SerDes channel simulation models and correlate them with test structures.
- Correlate ASIC PAM4 SerDes simulation results with measurements and work with component and ASIC vendors to improve model accuracy.
- Perform PCB timing analysis and work with board engineers and layout designers to implement signal integrity design rules.
- Develop and document layout and signal integrity design rules and checklists.
- Tune ASIC PAM4 SerDes parameters to improve serial-link design margins.
- Perform signal integrity DVT measurements on boards and correlate simulations with DVT measurements.
- Provide technical assessments of projects to the signal integrity management team.
Benefits
- Comprehensive benefits supporting physical, financial, and emotional wellbeing.
- Programs to support personal and professional development and career goals.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
