Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity

Marvell Technology • Santa Clara, CA

5d • $177,820 - $266,400

About The Position

Marvell is seeking a Senior Principal Engineer specializing in Signal Integrity and Power Integrity (SI/PI) for its U.S. Customer Solutions Group. This senior individual-contributor role serves as the technical authority for ensuring that customer platforms based on Marvell Ethernet Switch and UALink silicon meet high performance and quality standards, from early prototypes through mass production. The role has significant customer and ODM visibility and focuses on applying SI/PI practices that deliver robust performance at production scale.

The engineer will own SI/PI work across customer platforms, including layout and routing guidelines, post-silicon channel extraction and simulation, compliance testing, SerDes tuning guidance, and review of customer power-delivery-network designs. They will provide hands-on lab support for bring-up and production ramp, help define and validate reference designs, and relay customer and field learnings to Marvell silicon, packaging, and platform engineering teams. The role also contributes to product definition and roadmap planning and helps shape SI/PI approaches for current 112G and 224G PAM4 SerDes designs and future 448G systems.

The position involves close collaboration with customer engineering teams, ODMs, and Marvell teams across silicon design, packaging, board and system hardware, software, and operations. It includes developing and delivering technical training, mentoring engineers, and representing Marvell in customer briefings, executive reviews, and industry forums. Travel to customer sites, ODMs, and labs is required as needed, typically on a project-driven rather than continuous basis.

Requirements

• PhD, Master's, or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 15 or more years of experience in hardware design, development, and validation of high-speed networking or compute systems; exceptionally talented candidates with fewer years and demonstrated mastery are encouraged to apply.
• 10 or more years of focused signal integrity and power integrity experience on high-speed SerDes platforms, from 25G NRZ through 112G/224G PAM4; exceptionally talented candidates with fewer years and demonstrated mastery are encouraged to apply.
• Demonstrated expertise across the SI lifecycle, including channel modeling and budgeting, layout and stack-up guideline definition, post-layout extraction and simulation, design-fix recommendations, and compliance and tuning guidance.
• Ability to independently run and review PDN simulations covering impedance, IR drop, decoupling, transient response, and droop, and translate results into customer guidance.
• Fluency with leading SI/PI EDA toolchains such as Ansys HFSS/SIwave and Cadence Sigrity/Clarity/PowerSI, or equivalent, and ability to use the tools required by a project.
• Hands-on lab expertise with VNAs, BERTs, real-time and sampling oscilloscopes, TDR, jitter analyzers, and high-speed compliance test kits, with proven debug capability in customer and internal lab environments.
• Customer-facing experience supporting complex technical engagements and resolving real-world deployment issues.
• Demonstrated ability to develop and deliver technical training content to engineering audiences.
• Excellent communication skills and ability to influence senior customer engineering teams, ODM engineers, and internal stakeholders across disciplines and geographies.

Nice To Haves

• Direct experience with Ethernet switch platforms and/or emerging open AI fabric standards and architectures.
• Experience supporting SI/PI for platforms targeting megascale data center deployments at production volume.
• Background in reference platform SI/PI definition and customer enablement for silicon-based solutions.
• Familiarity with ODM/CM design and qualification flows, including DFM/DFT, reliability testing, and high-volume manufacturing variability.
• Experience defining SerDes tuning methodologies and correlating simulation, lab, and field-telemetry data.
• Familiarity with chip-to-module, copper cable, and connector ecosystems relevant to high-speed Ethernet and AI fabric channels.
• Track record of influencing silicon and platform roadmaps based on SI/PI insights from customer and field deployments.

Responsibilities

• Serve as the senior SI/PI technical authority for customer platforms built on Marvell Ethernet switches and UALink silicon, from channel definition through mass-production qualification.
• Define and maintain layout and routing guidelines for high-speed SerDes channels, power delivery networks, and sensitive analog interfaces, and drive their adoption with customers, ODMs, and internal teams.
• Perform post-silicon channel extraction, full-channel simulation, and what-if analysis on customer board designs; recommend layout and stack-up fixes to improve design margins.
• Lead compliance testing and lab characterization, including BER/SER, eye-opening margins, jitter, return loss, and crosstalk, and translate results into design and SerDes-tuning guidance.
• Provide customer SerDes tuning guidance based on simulation, lab measurements, and field telemetry, and partner with Marvell silicon teams to refine tuning methodologies.
• Run and review power integrity simulations covering PDN impedance, IR drop, decoupling effectiveness, transient response, and droop; guide customers on robust PDN architectures for high-current ASICs.
• Translate customer power needs and constraints into feedback for Marvell silicon, packaging, and platform engineering teams.
• Engage directly with ODMs on SI/PI guidance, design reviews, and qualification activities, in partnership with the global Customer Solutions Group and internal engineering teams.
• Support definition and validation of reference designs for new Marvell silicon, owning SI/PI work from early channel budgeting through customer release.
• Provide hands-on lab debug expertise during customer bring-up and production ramp using VNAs, BERTs, real-time scopes, TDR equipment, jitter analyzers, and compliance test kits.
• Develop and deliver SI/PI training to customers, ODMs, and internal Marvell teams on high-speed design practices, simulation methodology, and lab debug techniques.
• Provide technical leadership on 112G and 224G PAM4 SerDes designs and help shape Marvell's SI/PI approach for next-generation 448G systems.
• Partner with Marvell Silicon Design, Packaging, Board/System HW, Software, and Operations teams to deliver integrated solutions.
• Contribute real-world SI/PI insights to product definition, roadmap planning, architecture, and marketing discussions.
• Represent Marvell's SI/PI expertise in customer briefings, executive reviews, and industry technical forums.
• Set the SI/PI technical bar across strategic customer engagements and ensure designs are production-robust, not merely compliant.
• Mentor engineers and lead SI/PI training for customers, ODMs, and internal stakeholders.
• Travel to customer sites, ODMs, and labs as needed, typically on a project-driven basis.

Benefits

• Eligible to participate in Marvell's bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Mental health resources.
• Recognition and service awards.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal