Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity

Marvell Technology • Santa Clara, CA

6d • $177,820 - $266,400

About The Position

Marvell is seeking a Senior Principal Engineer for Signal Integrity and Power Integrity to serve as the senior technical authority for customer platforms built on Marvell Ethernet Switch and UALink silicon. This senior individual-contributor role supports customers and ODMs from early architecture and prototyping through qualification, production ramp, and mass production, with a focus on ensuring high performance, quality, and production-robust margins.

The engineer will implement SI/PI practices across Marvell-based platforms, including defining layout and routing guidelines; conducting post-silicon channel extraction and simulation; leading compliance testing and lab characterization; advising on SerDes tuning; and reviewing power delivery network designs. The role also provides customer and ODM design guidance, supports reference-design definition and validation, and feeds platform and field insights back to Marvell silicon, packaging, and hardware engineering teams to improve products and inform future roadmaps. The position contributes technical leadership for current 112G and 224G PAM4 SerDes designs and Marvell's approach to next-generation 448G systems and open AI fabric standards.

This position is part of Marvell's U.S. Customer Solutions Group, which works closely with infrastructure customers and internal engineering teams to turn Marvell silicon into deployable platforms. The role includes mentoring and technical training, customer briefings and executive reviews, and travel to customer sites, ODMs, and labs as needed, typically on a project-driven basis.

Requirements

• PhD, Master's, or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 15 or more years of experience in hardware design, development, and validation of high-speed networking or compute systems.
• 10 or more years of focused signal integrity and power integrity experience on high-speed SerDes platforms, from 25G NRZ through 112G/224G PAM4.
• Demonstrated expertise across the SI lifecycle: channel modeling and budgeting, layout and stack-up guideline definition, post-layout extraction and simulation, design-fix recommendations, and compliance and tuning guidance.
• Ability to independently run and review PDN simulations covering impedance, IR drop, decoupling, transient response, and droop, and translate results into customer guidance.
• Fluency with leading SI/PI EDA toolchains, such as Ansys HFSS/SIwave and Cadence Sigrity/Clarity/PowerSI, or equivalent, and ability to use the tools required by a project.
• Hands-on lab expertise with VNAs, BERTs, real-time and sampling oscilloscopes, TDR equipment, jitter analyzers, and high-speed compliance test kits, with proven debug capability in customer and internal lab environments.
• Customer-facing experience supporting complex technical engagements and resolving real-world deployment issues.
• Ability to develop and deliver technical training content to engineering audiences.
• Excellent communication skills and ability to influence senior customer engineering teams, ODM engineers, and internal stakeholders across disciplines and geographies.

Nice To Haves

• Direct experience with Ethernet switch platforms and/or emerging open AI fabric standards and architectures.
• Experience supporting SI/PI for platforms targeting megascale data center deployments at production volume.
• Background in reference-platform SI/PI definition and customer enablement for silicon-based solutions.
• Familiarity with ODM/CM design and qualification flows, including DFM/DFT, reliability testing, and high-volume manufacturing variability.
• Experience defining SerDes tuning methodologies and correlating simulation, lab, and field-telemetry data.
• Familiarity with chip-to-module, copper cable, and connector ecosystems relevant to high-speed Ethernet and AI fabric channels.
• Track record of influencing silicon and platform roadmaps using SI/PI insights from customer and field deployments.
• Candidates with fewer years of experience who demonstrate mastery through impactful project work, deep technical contributions, or industry recognition are encouraged to apply.

Responsibilities

• Serve as the senior SI/PI technical authority for customer platforms built on Marvell Ethernet switches and UALink silicon, from channel definition through mass-production qualification.
• Define and maintain layout and routing guidelines for high-speed SerDes channels, power delivery networks, and sensitive analog interfaces, and drive their adoption with customers, ODMs, and internal teams.
• Perform post-silicon channel extraction, full-channel simulation, and what-if analysis on customer board designs, and recommend layout and stack-up changes to improve design margins.
• Lead compliance testing and lab characterization, including BER/SER, eye-opening margins, jitter, return loss, and crosstalk; translate results into actionable design and SerDes-tuning guidance.
• Provide customers with SerDes tuning guidance based on simulations, lab measurements, and field telemetry, and partner with Marvell silicon teams to refine tuning methodologies.
• Run and review power integrity simulations covering PDN impedance, IR drop, decoupling effectiveness, transient response, and droop; guide customers on robust PDN architectures for high-current ASICs.
• Translate customer power needs and constraints into structured feedback for Marvell silicon, packaging, and platform engineering teams.
• Engage directly with ODMs on SI/PI guidance, design reviews, and qualification activities, in partnership with the global Customer Solutions Group and internal engineering teams.
• Support definition and validation of reference designs for new Marvell silicon, owning the SI/PI work from early channel budgeting through customer release.
• Provide hands-on lab debug support during customer bring-up and production ramp.
• Develop and deliver SI/PI training for customers, ODMs, and internal Marvell teams on high-speed design practices, simulation methodology, and lab debug techniques.
• Provide technical leadership on 112G and 224G PAM4 SerDes designs and help shape the SI/PI approach for next-generation 448G systems.
• Partner with Silicon Design, Packaging, Board/System Hardware, Software, and Operations teams to deliver integrated solutions.
• Contribute real-world SI/PI insights to product definition, roadmap planning, architecture, and marketing discussions.
• Represent Marvell SI/PI expertise in customer briefings, executive reviews, and industry technical forums.
• Set the SI/PI technical bar across strategic customer engagements, mentor engineers, and serve as a technical interface among customers, ODMs, silicon teams, and internal hardware engineering.

Benefits

• Eligible to participate in bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Employee stock purchase plan with a 2-year look back.
• Family support programs.
• Mental health resources.
• Recognition and service awards.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior