Advanced Package Design Engineer – Principal Engineer

Qualcomm • San Diego, CA

1d • $210,000 - $315,000

About The Position

Qualcomm Technologies, Inc. is seeking a Principal Engineer to build and lead a 2.5D/3D Advanced Package Design team within CHS, supporting next-generation high-performance compute and datacenter products. The role leads development, deployment, and continuous improvement of scalable package design methodologies and flows, and directs package architecture, design implementation, verification, and release for complex multi-die products.

The position combines hands-on expertise in silicon interposers, silicon bridges, chiplets, HBM, and advanced substrates with leadership of engineering teams and production-quality design flows. The Principal Engineer evaluates and integrates industry EDA and foundry ecosystems, including TSMC 3Dblox, and partners with EDA vendors, foundries, OSATs, substrate suppliers, and internal engineering teams to establish robust, automated, signoff-ready design solutions. The role requires strategic leadership and the ability to turn emerging 2.5D/3D technologies into repeatable product execution.

The role also establishes team capabilities and design-flow infrastructure, guides package architecture and physical implementation, governs verification and signoff, and leads execution from feasibility through tapeout and production release. It represents advanced package design in executive and program reviews and coordinates cross-functional and external partners to address technical risks, manufacturing requirements, and production readiness.

Requirements

• Proven experience building and leading advanced package design, 3DIC methodology, package CAD, or physical-design teams, including hiring, mentoring, performance development, resource planning, and technical-lead development.
• Deep knowledge of 2.5D/3D integration technologies and structures, including silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, HBM integration, chiplets, die stacking, micro-bumps, hybrid bonding, and package assembly.
• Hands-on experience defining or deploying production 2.5D/3D design flows covering planning, implementation, verification, multi-physics analysis, design-data handoff, tapeout, and release.
• Understanding of industry 3DIC EDA ecosystems and foundry design enablement, including TSMC 3Dblox concepts, die/package assembly description, hierarchy, connectivity, constraints, design reuse, and cross-tool interoperability.
• Expertise with relevant package and 3DIC implementation environments from Cadence, Siemens EDA, Synopsys, or equivalent vendors; strong understanding of constraint management, database integration, automation, and signoff.
• Expert knowledge of advanced package physical design, including multi-die floorplanning, HBM placement, bump and interface planning, pinout optimization, high-density routing, interposer/bridge implementation, substrate stackup, power/ground planning, and board escape.
• Strong understanding of package-level SI/PI and electromagnetic effects for HBM, UCIe and other die-to-die interfaces, PCIe, DDR, high-speed SerDes, clocks, and high-current power delivery.
• Working knowledge of package thermal-mechanical and reliability analysis, including warpage, die/interposer stress, material interactions, thermal interfaces, assembly process windows, failure mechanisms, and qualification requirements.
• Experience establishing DRC, DFM, ERC, connectivity, extraction, multi-physics, and release-signoff methodology using foundry, OSAT, substrate, and internal rules.
• Strong scripting and automation mindset, with experience developing maintainable flows using languages and environments such as Python, Tcl, Perl, shell, APIs, workflow orchestration, regression systems, and version control.
• Ability to assess EDA tool capability, benchmark competing solutions, define requirements, drive vendor roadmaps, resolve tool and methodology gaps, and establish production-support models.
• Excellent executive communication, technical decision-making, cross-functional influence, supplier engagement, and ability to lead globally distributed teams through complex, ambiguous engineering challenges.
• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field and 8+ years of System/Package Design/Technology Engineering or related work experience; or a master's degree in one of these fields and 7+ years; or a Ph.D. in one of these fields and 6+ years.

Nice To Haves

• Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, Mechanical Engineering, Materials Science, or a related field, with 15+ years of semiconductor package design, 3DIC, physical-design methodology, or related experience; equivalent industry experience may be considered.
• Demonstrated record of building and managing a substantial advanced package design or methodology organization supporting multiple complex products and technology generations.
• Proven ownership of production 2.5D/3D package design methodology and implementation for AI, HPC, datacenter, accelerator, networking, or other high-performance multi-die products.
• Direct experience delivering packages that integrate compute SoCs or chiplets with HBM using silicon-interposer, silicon-bridge, RDL-interposer, or vertically integrated 3D solutions.
• Experience integrating foundry reference flows and assembly-description frameworks such as TSMC 3Dblox into internal design, analysis, verification, and tapeout environments.
• Extensive experience with industry-leading 2.5D/3D IC design, implementation, and verification environments, including Cadence Innovus, Integrity 3D-IC, Allegro Package Designer (APD), Virtuoso, Siemens Calibre 3DSTACK, and comparable Synopsys and Ansys 3DIC solutions.
• Demonstrated experience evaluating, integrating, and deploying multi-vendor EDA tools within foundry-qualified 2.5D/3D design flows, including familiarity with assembly-description and interoperability frameworks such as TSMC 3Dblox.
• Experience establishing cross-domain chip-package-board co-design and multi-physics workflows spanning electrical, thermal, mechanical, reliability, test, manufacturing, and system constraints.
• Experience working directly with leading foundries, OSATs, substrate suppliers, assembly partners, EDA vendors, and IP providers to evaluate, develop, validate, qualify, and ramp advanced packaging solutions.
• Understanding of HBM, UCIe or other die-to-die protocols, PCIe, DDR, and high-speed SerDes, including package architecture, layout, extraction, SI/PI, and verification implications.
• Demonstrated ability to define methodology roadmaps, prioritize investments, establish measurable design-flow quality and productivity targets, and drive deployment across a global engineering organization.
• Demonstrated innovation through advanced package solutions, EDA methodologies, automation, patents, publications, industry working groups, or standards engagement.

Responsibilities

• Build, manage, mentor, and grow a high-performing 2.5D/3D package design team, including package architects, physical-design engineers, methodology developers, CAD/automation engineers, and technical leads.
• Own the strategy, roadmap, architecture, implementation, qualification, and deployment of end-to-end 2.5D/3D package design methodologies and flows for complex multi-die products.
• Develop standardized, scalable, reusable flows for package planning, die/chiplet assembly definition, floorplanning, HBM and chiplet placement, bump and interface planning, interposer and bridge design, substrate design, verification, signoff, tapeout, and release.
• Lead implementation of 2.5D/3D packages using silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, hybrid-bonded or vertically stacked die, HBM, and emerging integration technologies.
• Evaluate and deploy foundry and EDA-vendor 3DIC solutions, including TSMC 3Dblox-compatible methodologies and interoperable implementation, analysis, verification, data-exchange, and signoff flows.
• Define tool requirements and drive technical alignment with Cadence, Siemens EDA, Synopsys, Ansys, foundries, and other ecosystem partners to close capability gaps and improve productivity, quality, and scalability.
• Establish design-flow architecture, data models, interfaces, automation frameworks, configuration management, regression testing, release management, metrics, documentation, and user support.
• Guide package architecture and physical implementation across die/chiplet floorplanning, bump maps, HBM placement, die-to-die interfaces, connectivity, routing topology, layer-stack optimization, power/ground distribution, board escape, and package-size optimization.
• Define and govern package verification and signoff requirements, including connectivity, DRC, DFM, ERC, LVS-equivalent checks, assembly-rule compliance, package extraction, SI/PI, thermal, mechanical, reliability, and manufacturability reviews.
• Partner with silicon architecture, SoC physical design, DFT, SI/PI, thermal, mechanical, board, product engineering, manufacturing, and supply-chain teams to enable concurrent chip-package-board-system co-design.
• Lead package design execution from feasibility through tapeout and production release; establish design reviews, technical checkpoints, risk tracking, escalation paths, and closure criteria across product programs.
• Drive methodology correlation and validation using representative test cases and product designs; ensure flow readiness, repeatability, traceability, and robustness before broad production adoption.
• Engage foundries, OSATs, substrate suppliers, and assembly partners to understand technology structures, process constraints, design rules, assembly requirements, test considerations, reliability risks, yield limiters, and production-readiness requirements.
• Develop team capability plans, hiring profiles, training, succession plans, and technical career paths; coach senior engineers and establish subject-matter experts for key 2.5D/3D design domains.
• Represent advanced package design in executive and program reviews, communicating roadmap decisions, architecture tradeoffs, methodology readiness, resource requirements, execution status, technical risks, and mitigation plans.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Competitive benefits package designed to support success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Principal