About The Position

Apple's Advanced Packaging Program is seeking an engineer to drive package integration and technology development for next-generation products. The role contributes to advanced packaging technologies that enable Apple's silicon performance and involves working with engineers to solve complex integration challenges and bring packaging innovations from concept to mass production. The engineer is responsible for advanced packaging development and pathfinding, engaging with leading-edge foundries and OSATs to lead package integration, process definition, and architecture efforts. The role defines specifications, drives process windows, and establishes advanced packaging solutions including 2.5D/3D packaging, hybrid bonding, and high-density wafer-level interconnects.

Requirements

  • Bachelor of Science degree and 10+ years of relevant industry experience.
  • Deep technical expertise in advanced packaging architectures and foundry processes.
  • Hands-on experience reviewing GDS/layout data, performing physical verification (DRC/LVS), and using IC layout/viewing tools such as Calibre, Virtuoso, or KLayout.
  • Proven track record managing foundry partners, defining DOEs, driving NPI engineering builds, and analyzing inline/end-of-line metrology and electrical test data.
  • Background in packaging physics and multi-domain interactions, including thermo-mechanical effects, warpage, thin-wafer handling, reliability, and SI/PI fundamentals.
  • Strong problem-solving, analytical rigor, and communication skills to interface effectively with cross-functional and overseas foundry/OSAT partners.

Nice To Haves

  • MS or PhD degree.
  • 6+ years of relevant industry experience in advanced wafer-level packaging.

Responsibilities

  • Drive advanced packaging development and pathfinding.
  • Engage with leading-edge foundries and OSATs to lead package integration, process definition, and architecture efforts.
  • Define specifications, drive process windows, and establish advanced packaging solutions such as 2.5D/3D, hybrid bonding, and high-density wafer-level interconnects.
  • Manage foundry partners, define DOEs, drive NPI engineering builds, and analyze inline/end-of-line metrology and electrical test data.
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