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Research Scientist - Loop Engineering and AI Infrastructure

SK hynix memory solutions America Inc.•San Jose, CA
•Onsite

About The Position

We are hiring a full-time research scientist. Depending on your qualifications, the job is loop engineering, AI infrastructure research, or both. Loop engineering is the design and study of closed-loop flows that automate, optimize, and explore SoC designs. These are AI-assisted hardware/software co-design flows. CHIA, from UC Berkeley, is one example of a framework you may use. AI infrastructure research is full-stack design and optimization of AI systems from storage devices to the host: how memory-device noise affects AI performance, where the system bottlenecks, and which compute-memory architectures are worth building. You will own the research questions, methods, and written results.

Requirements

  • Bachelor’s, master’s, or Ph.D. in electrical engineering, computer engineering, or computer science. A bachelor’s degree should include research depth in computer architecture, computer systems, VLSI, or electronic design automation.
  • A record of taking a research question to a measured, written result.
  • Strong in Python.
  • For a loop-engineering assignment: Experience automating an SoC, RTL, or physical-design flow, including design-space exploration or closed-loop optimization.
  • Ability to design interfaces between design tools so a flow can be reused.
  • For an AI infrastructure assignment: Research on the path from storage or memory devices to a host running an AI workload, and on how device behavior, system bottlenecks, or compute-memory architecture affect AI performance.

Nice To Haves

  • Hands-on experience with an AI-assisted hardware/software co-design loop framework, such as CHIA, or with another agentic or scripted flow.
  • Proficiency with Chisel, XLS, or RISC-V SoC integration, and with RTL simulation or FPGA prototyping.
  • Experience with commercial ASIC flows, and with reading timing, power, and area reports.
  • Experience with architecture simulators.
  • Background in memory or storage reliability: device noise, ECC, endurance, or error models.
  • Papers or patents in computer architecture, VLSI CAD, or hardware/software co-design.

Responsibilities

  • Establish best practices for SoC design automation, optimization, and design-space exploration, and make them the way the team runs design studies.
  • Design and implement co-design loops whose steps run SoC tools, simulators, software builds, physical-design feedback, and AI agents, and whose outputs feed the next iteration.
  • Build those flows with the languages and tools the study needs, including Chisel and XLS, simulators, software builds, and ASIC or FPGA CAD.
  • Measure whether the designs a loop produces are correct, and compare them on power, speed, silicon area, or how well the target workload runs.
  • Record which design was chosen, what the search cost, and enough detail that someone else can rerun the study and see why a run failed.
  • Study AI system design from storage and memory devices through controllers, interconnects, and the host software path used by training and inference.
  • Measure how device noise and non-idealities (read and write noise, variation, retention, disturb, and error rates) affect model quality, tail latency, throughput, and energy.
  • Quantify bottlenecks in capacity, bandwidth, latency, power, and data movement, and state what they imply for architecture.
  • Evaluate compute-memory architectures such as near-memory and in-memory compute, computational storage, and disaggregated memory.

Benefits

  • medical
  • dental
  • vision
  • life insurance
  • company 401(k) match
  • cafeteria
  • onsite gym

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What This Job Offers

Job Type

Full-time

Career Level

Entry Level

Education Level

Ph.D. or professional degree

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