Wireless SoC Design Engineer

Apple • Irvine, CA

1d

About The Position

Join Apple’s wireless silicon development team, which develops highly energy-efficient wireless silicon and technologies that enhance the product-level user experience. The organization spans RF/Analog, Systems/PHY/MAC, VLSI/RTL, emulation, design verification, test and validation, and firmware/software engineering.

As part of a small team, you will design CPU-based subsystems for high-performance, low-power wireless SoCs. You will work with SoC architects and IP developers to meet power, performance, and area goals, with particular focus on low-power metrics. The role also involves hardware/software/power partitioning with software, firmware, and platform teams; integrating industry-standard and custom hardware IP; and collaborating across disciplines to deliver high-quality designs on schedule.

You will write micro-architecture and design specifications, develop RTL in SystemVerilog, integrate IP blocks, optimize memories and hard macros, support verification at multiple levels, run static checks such as LINT, CDC, and RDC, and analyze and optimize area, timing, and power. The position is described as highly visible and central to ASIC design efforts for Apple products.

Requirements

• Bachelor of Science degree with 10+ years of relevant experience.
• Familiarity with the ASIC design flow.
• Knowledge of digital design, SoC architecture, and HDL languages such as Verilog.
• Experience writing micro-architecture specifications and translating them into designs.
• Exposure to design methodologies and industry-standard EDA tools.
• Experience with AXI/AHB bus fabric and processor subsystems.
• Understanding of UPF and low-power design and implementation techniques.
• Self-starter with a willingness to learn.

Responsibilities

• Write micro-architecture and design specifications.
• Code designs in SystemVerilog according to established design guidelines and own RTL development.
• Integrate IP blocks into SoCs and optimize required memories and hard macros.
• Support verification efforts at multiple levels.
• Check designs using static tools such as LINT, CDC, and RDC.
• Analyze and optimize area, timing, and power.
• Work with SoC architects and IP developers to meet power, performance, and area goals, particularly low-power goals.
• Participate in hardware/software/power partitioning discussions with software, firmware, and platform engineering teams.
• Collaborate with multidisciplinary groups to deliver designs on time and with high quality, incorporating checks at each stage of the design process.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior