Wireless SoC Design Engineer

Apple•San Diego, CA

About The Position

Join Apple’s wireless silicon development team, which develops wireless silicon with an emphasis on energy-efficient design and technologies that transform product experiences. The organization brings together teams spanning RF/analog, systems/PHY/MAC, VLSI/RTL, emulation, design verification, test and validation, and firmware/software engineering. In this role, you will work on a small team designing CPU-based subsystems for high-performance, low-power wireless SoCs. You will collaborate with SoC architects and IP developers to meet power, performance, and area goals for Apple devices, with particular focus on low-power metrics. You will participate in hardware/software/power partitioning discussions with software, firmware, and platform engineering teams, and integrate industry-standard and custom hardware IPs into SoCs. This visible role is central to ASIC design efforts and contributes to launching products.

Requirements

  • Bachelor’s degree.
  • Familiarity with the ASIC design flow.
  • Knowledge of digital design and SoC architecture.
  • Knowledge of HDL languages such as Verilog.

Nice To Haves

  • MSEE with some years of industry experience.
  • Experience writing micro-architecture specifications and converting them into designs.
  • Exposure to design methodologies and industry-standard EDA tools.
  • Experience with AXI/AHB bus fabric and processor subsystems.
  • Understanding of UPF and low-power design and implementation techniques.
  • Self-starter with a willingness to learn.

Responsibilities

  • Design CPU-based subsystems for high-performance, low-power wireless SoCs.
  • Work with SoC architects and IP developers to meet power, performance, and area goals, particularly low-power goals.
  • Participate in hardware/software/power partitioning discussions with software, firmware, and platform engineering teams.
  • Integrate industry-standard and custom hardware IPs into SoCs.
  • Collaborate across functional areas on ASIC design efforts.
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