SoC Physical Design Engineer

Apple

3d • Onsite

About The Position

As a member of our Physical Design group, you will take an integral part in bringing large scale SoCs to life, helping us deliver the next generation of Apple's ground-breaking products. You will own the physical design cycle at the partition/IP/Chip levels, including netlist to GDS implementation and verification. As a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.

Requirements

• 3+ years of experience in physical design of large-scale SoCs
• B.Sc / M.Sc Electric Engineering / Computer Engineering
• Extensive experience with one of the place & route tools (Synopsys / Cadence)
• Scripting and Programming experience using either TCL or Python or Perl, or known Shell scripting languages

Nice To Haves

• Knowledge in Verilog

Responsibilities

• Own the physical design cycle at the partition/IP/Chip levels, including netlist to GDS implementation and verification.
• Block level PnR, floor-planning, clock, power planning and distribution.
• Static Timing closure using commercial tools, Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise).

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level