SoC Physical Integration Engineer

Advanced Micro Devices, Inc•San Jose, CA

22h

About The Position

AMD’s Adaptive Embedded Computing Group (AECG) develops products that combine processors, neural engines, graphics processors, and adaptive computing technologies with programmable logic for edge computing applications. As a member of the SoC Physical Integration team, the engineer collaborates with Architecture, Design, CAD, Software, and Product Engineering teams across multiple geographies, contributing to the physical and electrical verification, integration, and tape-out of AMD SoC FPGA/ACAP devices. The position is located in San Jose, California, and is not eligible for visa sponsorship.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or an equivalent field.
Strong debugging, analytical, and problem-solving skills.
Proficiency in scripting languages such as Perl, Python, TCL, C-shell, Make, or other relevant scripting languages.
Experience working in Unix/Linux environments, including data management and job control.
Excellent written and verbal communication skills, with the ability to collaborate effectively across cross-functional and geographically distributed teams.

Nice To Haves

Solid understanding of FPGA architectures.
Hands-on experience with advanced process nodes, including leading-edge 2nm and 3nm technologies.
In-depth knowledge of 2.5D and 3D interposer technologies.
Hands-on experience with physical implementation using industry-standard physical design tools such as Virtuoso, ICC2, Fusion Compiler (FC), Innovus, or comparable tools.
Strong foundation in circuit design, including hands-on simulation experience with SPICE and Verilog.
Knowledge of or practical experience with Place and Route (P&R) tools and methodologies.

Responsibilities

Define and develop flows and methodologies for chip-level integration.
Develop tools and automation to enhance design verification and engineering efficiency.
Design, verify, and integrate FPGA/ACAP sub-blocks, including RTL and custom design.
Coordinate activities across design teams to enable seamless chip-level integration.
Execute chip-level physical verification.
Execute chip-level electrical verification.