Senior SoC Physical Layout & Full-Chip Integration Engineer

Intel Corporation•Austin, TX

2d•$122,440 - $232,190•Hybrid

About The Position

Join the Design Technology Platform (DTP) organization within Intel Foundry and help drive the development of the methodologies, physical layouts, and silicon platforms that enable next-generation semiconductor technologies. As a member of the X-Chip Full-Chip Integration team, you will play a key role in developing custom layout methodologies, leading full-chip physical integration, and driving physical verification and tapeout execution for advanced testchip and silicon lead vehicles on cutting-edge process technologies. This role is ideal for engineers who have a passion for custom layout design, advanced-node physical design methodologies, and solving complex physical integration challenges. You will work at the intersection of technology development, physical design, verification, and manufacturing, collaborating with experts across Intel Foundry to enable future process technologies and silicon solutions.

Requirements

Masters' degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience. OR a PhD’s degree in the same filed with 1+ years of industry experience.
Custom/analog/mixed-signal layout design experience in advanced technology nodes.
Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (such as Calibre or ICV), with a proven ability to solve complex, systemic layout errors.
Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

Nice To Haves

Experience with top-level floorplanning, RDL/bump planning, or backside power delivery (PowerVia) implementation.
Proven track record of collaborating with PDK and Technology Development teams on design rule definitions, test structure vehicles, or DRC suppression strategies.
Experience managing physical tapeout schedules, IP tracking matrices, and formal physical design Quality Assurance (QA) flows.
Familiarity with custom layout environments (such as Cadence Virtuoso) and translating custom databases into full-chip NDM flows.
Previous related work experience in a semiconductor foundry preferred.

Responsibilities

Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
Develop and enhance custom layout methodologies and physical design flows.
Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
Analyze advanced-node design rules and contribute to design enablement for emerging process technologies, including FinFET and Gate-All-Around (GAA) architectures.
Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages to improve design productivity and quality.
Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.