SoC Chip Lead
About The Position
We are looking for a senior SoC Chip Lead to join our San Jose office. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.
Requirements
- BS/MS/PhD in Electrical or Computer Engineering with 20+ years of FPGA/SoC design experience
- Established track record leading programs from concept to tape-out and production release
- Expertise in SystemVerilog, synthesis, and static timing analysis
- Deep expertise across SoC domains including High-speed interfaces, System Interconnects, Processor subsystems, and 2.5D/3D packaging and chiplet-based architectures
- Own system-level functional and performance modeling across SoC subsystems, ensuring RTL correlation and supporting emulation-based pre-silicon validation
- Define and own DFx methodology including scan, BIST, and manufacturing test from IP to chip level
- Experience debugging complex use cases through verification, emulation, and system validation
- Demonstrated ability to lead and grow geographically distributed, cross-functional engineering teams
- Strong written and oral communication skills with a history of executive-level presentations
Responsibilities
- Lead development of MCMs with FPGA and ASSPs utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures across multiple program generations
- Own chip tapeout and chip signoff with full accountability for chip quality
- Drive cross-functional technical leadership across multiple sites; translate product requirements into clear priorities, tradeoffs, and execution paths
- Partner with architects, RTL engineers, and software teams to evaluate architecture tradeoffs and drive hardware design decisions across the SoC
- Lead cycle-approximate performance modeling to enable architectural exploration ahead of RTL availability and accelerate early software development
- Quantify system-level tradeoffs across compute, memory bandwidth, and on-chip interconnect to shape reference architectures and inform long-term silicon strategy
- Own system-level debug spanning floor-planning, power distribution, clocking, timing closure, and SI/PI
- Engage with leading IP vendors to define and execute the IP roadmap; conduct competitive benchmarking
- Present project status and technology roadmaps to executive leadership, with a focus on new growth markets and opportunities
- Apply agentic AI methodologies to scale and accelerate design execution
Benefits
- healthcare and retirement plans
- paid time off
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Ph.D. or professional degree
