SOC Design Verification Engineer
About The Position
Apple is seeking a Wireless SOC Design Verification Engineer to contribute to development of energy-efficient wireless silicon. The role owns a meaningful verification scope across block, subsystem, and top-level SOC, taking it from test planning through coverage closure and signoff. The engineer works with architects, designers, and firmware engineers to create reusable, metric-driven verification environments and selects simulation, formal verification, or other suitable approaches for each design. Potential areas include the Power Management Unit, CPU subsystem, DMA, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY verification, radio integration, and peripherals such as SPI. The role includes verifying low-power design intent with UPF, end-to-end WiFi and Bluetooth traffic flows, and IP integration into the SOC. The engineer may deepen expertise in specific IPs and subsystems or expand across IPs and SOC integration. The team is also exploring AI-assisted verification for test generation, debugging, and coverage closure. Post-silicon bring-up support may be needed.
Requirements
- Bachelor’s degree and a minimum of 10 years of relevant industry experience.
- Hands-on experience across the verification cycle, including test planning, testbench implementation, test creation and debug, and coverage closure.
- Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
- Solid problem-solving and debugging skills in constrained-random verification.
- Understanding of digital logic design, SOC architecture, and microarchitecture.
- Experience taking at least one ASIC/SOC from concept through tape-out.
- Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
- Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
- Experience with low-power verification, UPF, boot-up, power-cycling, and hardware/firmware interaction.
- Experience with SystemVerilog Assertions (SVA) and/or formal tools such as JasperGold.
- Experience defining coverage space and writing coverage models.
- Experience with embedded CPU verification; programming in C/C++ or assembly.
- Scripting experience in Python or Perl.
- Excellent communication skills, a collaborative approach, and willingness to take on diverse challenges.
Nice To Haves
- Interest in applying AI/ML to verification workflows.
Responsibilities
- Partner with architects and designers early to develop detailed verification plans from specifications.
- Develop reusable block/IP and subsystem-level UVM testbenches and support IP integration into the SOC.
- Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure.
- Debug failures, including corner cases, and manage bug tracking through resolution.
- Verify low-power design intent using UPF within the assigned scope.
- Verify end-to-end WiFi and Bluetooth traffic flows from subsystem level through top-level SOC integration.
- Apply formal verification where appropriate.
- Build and improve automated regression flows and contribute to verification methodology.
- Explore and apply AI-assisted verification techniques to improve team productivity.
- Participate in verification reviews and uphold high coding-quality standards.
- Support post-silicon bring-up as needed.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
