SOC Design Verification Engineer

Apple•Irvine, CA

17h

About The Position

Apple’s wireless SOC organization develops wireless silicon, with a focus on energy-efficient designs and technologies that improve the product experience. The team spans RF/Analog, Systems/PHY/MAC, VLSI/RTL design and integration, emulation, design verification, test and validation, and firmware/software engineering. The Wireless SOC Design Verification Engineer owns a verification scope and is responsible for pre-silicon RTL verification at the block, subsystem, and top-level SOC. The role covers the verification process from test planning through coverage closure and signoff, working closely with architects, designers, and firmware engineers to build reusable testbenches and verification environments using metric-driven methods. Potential areas include the Power Management Unit, CPU subsystem, DMA, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY verification, radio integration, and peripherals such as SPI. The role uses simulation, formal verification, or other suitable approaches, and verifies low-power design intent using UPF within its scope. The engineer may deepen expertise in particular IPs and subsystems or broaden their work across IPs and full-SOC integration. The team is exploring AI-assisted verification for areas such as test generation, debug, and coverage closure. Responsibilities also include verifying end-to-end WiFi and Bluetooth traffic flows from subsystem through top-level SOC integration, improving automated regression flows and methodology, participating in verification reviews, maintaining coding quality, and supporting post-silicon bring-up as needed.

Requirements

Minimum of a bachelor’s degree.
Hands-on experience across the verification cycle, including test planning, testbench implementation, test creation and debug, and coverage closure.
Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
Strong problem-solving and debugging skills with constrained-random verification.
Understanding of digital logic design, SOC architecture, and microarchitecture.
Experience taking at least one ASIC/SOC from concept through tape-out.
Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
Excellent communication skills and ability to work as a teammate while taking on diverse challenges.

Nice To Haves

Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
Experience with low-power verification, UPF, boot-up, power-cycling, and hardware/firmware interaction.
Experience with SystemVerilog Assertions (SVA) and/or formal tools such as JasperGold.
Experience defining coverage space and writing coverage models.
Experience with embedded CPU verification and programming in C/C++ or assembly.
Scripting experience in Python or Perl.
Interest in applying AI/ML to verification workflows.

Responsibilities

Partner with architects and designers early to develop detailed verification plans from specifications, before RTL is available.
Develop reusable block/IP and subsystem-level UVM testbenches and support IP integration into the SOC.
Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure.
Debug failures, including corner cases, and manage bugs through resolution.
Verify low-power design intent using UPF within the assigned scope.
Verify end-to-end WiFi and Bluetooth traffic flows from subsystem level through top-level SOC integration.
Apply formal verification where appropriate.
Build and improve automated regression flows and contribute to verification methodology.
Explore and apply AI-assisted verification techniques to improve team productivity.
Participate in verification reviews and uphold high coding-quality standards.
Support post-silicon bring-up as needed.