About The Position

The UDV / HW Design Verification Engineer works on-site at the Dallas R&D Lab, planning and conducting hardware verification on units, analyzing issues, and reporting results to engineering teams. The role covers verification planning from product and design requirements through unit bring-up, functional verification, RF and electrical performance checks, issue analysis, and release-readiness reporting. The engineer maintains requirement-to-test traceability and test coverage and may support the factory when needed.

Requirements

  • Hands-on experience in hardware or unit design verification.
  • Strong knowledge of RF and electrical measurements and laboratory instruments.
  • Experience in test planning, test case design, and test automation.
  • Skills in debugging, fault isolation, and root-cause analysis.
  • Experience with verification reports and defect tracking.
  • Experience with Python or similar scripting for test automation.
  • Knowledge of PA / RF radio hardware.
  • Good communication and documentation skills.
  • Bachelor’s or Master’s degree in Electronics, Electrical, RF Engineering, or a related field is listed as the preferred qualification.
  • 5–8 years of experience is listed.

Nice To Haves

  • Bachelor’s or Master’s degree in Electronics, Electrical, RF Engineering, or a related field.
  • 5–8 years of experience.

Responsibilities

  • Create verification plans from product and design requirements.
  • Define test scope, test cases, test methods, and acceptance criteria.
  • Set up the test environment and operate measurement equipment.
  • Perform unit bring-up and functional verification.
  • Verify RF and electrical performance, including operating and corner conditions.
  • Analyze results, run regression tests, isolate faults, and identify root causes.
  • Report defects and verify corrective actions.
  • Prepare verification reports and release-readiness evidence; support the factory if needed.
  • Maintain requirement-to-test traceability and test coverage.
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