Synthesis & Static Timing Analysis (STA) Engineer

Voltai • Palo Alto, CA

7d

About The Position

Voltai is developing world models and agents that learn, evaluate, plan, experiment, and interact with the physical world, beginning with hardware, electronics systems, and semiconductors. In this role, you will own the path from RTL to a timing-clean netlist and close timing on silicon programs with leading semiconductor companies. You will also help Voltai’s AI learn to write constraints, diagnose timing violations, and close timing.

Requirements

• At least 5 years of synthesis and STA experience on production tapeouts.
• Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
• Strong SDC skills, including clocks, exceptions, generated clocks, and multi-mode constraints.
• Experience with logic equivalence checking using Formality or Conformal.
• Strong Tcl and Python scripting skills.

Nice To Haves

• Advanced-node experience at 7nm and below.
• Experience with ECO flows and timing signoff methodology.
• Interest in AI-assisted design tools.

Responsibilities

• Own logic synthesis and constraint development (SDC) for blocks and full chips.
• Drive timing closure across corners and modes, working with RTL and physical design teams.
• Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
• Perform logic equivalence checking between RTL and netlist.
• Build automation to make synthesis and timing flows faster and more reliable.
• Evaluate AI-generated constraints and timing fixes, and help define what good looks like.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed