Synthesis & STA Engineer – High-Speed SerDes

Astera Labs•San Jose, CA

13h•$160,000 - $200,000

About The Position

As an Astera Labs Synthesis & STA Engineer – High-Speed SerDes, you will plan, coordinate, and execute design support for high-speed analog/mixed-signal SerDes and connectivity ASICs used by cloud service providers, server OEMs, and network OEMs. The role owns logic synthesis and static timing analysis across the digital portions of mixed-signal SerDes PHY designs, applying deep expertise in mixed-signal integration and collaborating with analog, RTL, physical design, and verification teams to achieve robust timing closure at advanced process nodes. The engineer will drive synthesis optimization, develop and validate timing constraints, manage multi-mode/multi-corner analysis, and support timing closure from synthesis through sign-off. Responsibilities also include hierarchical timing analysis, timing debug and ECO guidance, automation of large-scale STA flows, and close collaboration on clocking, power domains, and analog/digital interface timing.

Requirements

Bachelor's degree in Electrical Engineering or Computer Science.
At least 8 years of experience in synthesis, timing-constraint development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications.
Strong proficiency in writing and debugging SDC constraints, with a deep understanding of clock modeling, generated clocks, clock-domain crossings, and exception handling.
Expertise in STA methodology and block- and full-chip-level timing closure using Synopsys PrimeTime and/or Cadence Tempus.
Strong knowledge of synthesis, place-and-route, extraction, and equivalence-checking flows such as Formality or Conformal in advanced nodes (5nm/3nm and below).
Proficiency with Cadence and/or Synopsys physical-design and STA toolchains.
Strong scripting ability in Tcl, Python, or Perl.
Ability to work independently, prioritize effectively, and maintain a professional, customer-focused mindset.

Nice To Haves

Master's degree.
Direct experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY digital-controller and DSP timing challenges.
Understanding of analog/mixed-signal integration concerns, including analog-digital interface timing, PLL/DLL/CDR clock structures, and level-shifter/isolation-cell constraints.
Knowledge of ECO methodologies, DFT tools, and test-coverage analysis for mixed-signal designs.
Experience working with IP vendors on RTL and hard-macro integration, including Liberty (.lib), LEF, and behavioral-model characterization.
SystemVerilog or Verilog proficiency.
Familiarity with power-aware synthesis and STA, including UPF/CPF flows.
Experience with high-speed clocking architectures and multi-rate clock-domain management typical of SerDes designs.

Responsibilities

Perform RTL synthesis and optimize area, power, and timing for digital controller and DSP blocks in high-speed SerDes PHY designs.
Author, develop, and validate SDC constraints, including clock definitions, generated clocks, multi-frequency and multi-mode constraints, I/O delays, false paths, multicycle paths, and SerDes-specific clock-domain crossing exceptions.
Set up and manage MMMC environments for STA across process, voltage, and temperature corners.
Drive timing closure from synthesis through sign-off for digital blocks within mixed-signal SerDes IP and full-chip SoC integration.
Define and manage I/O timing budgets and interface constraints at analog/digital boundaries in hierarchical mixed-signal designs.
Apply sign-off methodologies at TSMC 5nm/3nm and below, including OCV/AOCV/POCV and relevant PVT effects.
Use ETM/ILM libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks, balancing runtime and accuracy.
Provide timing feedback at block and full-chip levels, including root-cause analysis, timing debug, and ECO guidance.
Manage large-scale MMMC STA runs through automation, partitioning, and efficient resource use; develop scripts and flows to improve turnaround time.
Generate and validate timing ECOs with physical design, analog, and RTL teams to close high-speed data-path and clock-path issues.
Partner with analog/mixed-signal design, SerDes architecture, implementation, and verification teams to drive timing convergence and provide sign-off expertise for PHY- and chip-level integration.
Collaborate on clock-tree and power-domain strategies for SerDes digital blocks, including compatibility with PLL/CDR-generated clocks and multi-supply domains.