Static Timing Analysis Design Engineer / Physical Design

NXP Semiconductors•Austin, TX

About The Position

The Static Timing Analysis Design Engineer will own end-to-end timing constraints and static timing analysis for advanced semiconductor products and complex SoC designs. The role spans initial constraint development and timing correlation in early design stages through final timing signoff, working with implementation engineers from synthesis through timing closure. The engineer will debug failing timing paths, provide timing feedback throughout the design process, and develop automated and manual timing engineering changes (ECOs). The position also contributes to team and organizational development, methodology improvements, and cross-functional collaboration. It supports post-silicon bring-up, yield improvement, and production ramp activities. The work focuses on timing closure for flagship SoCs at advanced technology nodes, with direct impact on silicon success and product competitiveness.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
3–6 years of experience in ASIC/SoC timing analysis.
Strong knowledge of industry STA tools, including Synopsys flows.
Expertise in STA and signoff methodologies.
Experience with timing ECO generation, automated and manual.
Experience developing and validating constraints.
Experience with advanced-node implementation (≤16nm / 5nm).
Scripting skills in Python, TCL, and Perl.
Familiarity with using AI to generate scripts.
Strong communication skills.

Nice To Haves

Experience in high-reliability SoCs.
Exposure to AI-driven design methodologies and automation.

Responsibilities

Own end-to-end timing constraints and timing signoff.
Create and validate timing constraints.
Work with Frontend, IP, and DFT teams to validate constraints and resolve timing issues.
Collaborate with implementation owners and the Full Chip STA team to close timing.
Perform timing correlation and timing-path debugging from synthesis through timing signoff.
Provide timing feedback during all design stages.
Create automated and manual timing fixes for implementation.
Participate in career development and team organization development.
Provide leadership with feedback on methodology enhancements to improve scalability, productivity, and design quality.
Support post-silicon bring-up, yield improvement, and production ramp activities.